Patents by Inventor Miwako Suzuki

Miwako Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410938
    Abstract: According to one embodiment, a semiconductor package includes a semiconductor chip, a sealing resin that has a flat plate shape and seals the semiconductor chip inside, a first electrode that includes a first mounting surface exposed on a first main face of the sealing resin, a second electrode that includes a second mounting surface exposed on the first main face, and a groove provided on the first main face. The first mounting surface includes a first end portion arranged in an inner region of the first main face and opposed to the second electrode. The groove includes a first connection portion connected to the first end portion, and a second connection portion connected to a lateral face of the sealing resin.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 9, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Miwako Suzuki
  • Publication number: 20220077308
    Abstract: A semiconductor device comprises a substrate of a first type, a drift layer of the first type, a plurality of base layers of a second type, a first electrode, an insulating layer, a second electrode, and a third electrode. The drift layer is formed on the substrate. The plurality of base layers is periodically formed extending in a direction in a surface of the drift layer. The first electrode is selectively formed extending in the direction in the surface of the base layers. The insulating layer is formed of an oxide film on the drift layer and on the base layer. The second electrode is formed extending in the direction with at least a part thereof overlapping with the first electrode via the oxide film. The third electrode is formed extending in the direction on the drift layer via the oxide film, between the second electrodes in the insulating layer.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 10, 2022
    Inventor: Miwako SUZUKI
  • Publication number: 20210280532
    Abstract: According to one embodiment, a semiconductor package includes a semiconductor chip, a sealing resin that has a flat plate shape and seals the semiconductor chip inside, a first electrode that includes a first mounting surface exposed on a first main face of the sealing resin, a second electrode that includes a second mounting surface exposed on the first main face, and a groove provided on the first main face. The first mounting surface includes a first end portion arranged in an inner region of the first main face and opposed to the second electrode. The groove includes a first connection portion connected to the first end portion, and a second connection portion connected to a lateral face of the sealing resin.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 9, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Miwako SUZUKI
  • Patent number: 9236468
    Abstract: According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miwako Suzuki, Norio Yasuhara
  • Publication number: 20150262915
    Abstract: According to an embodiment, a semiconductor device includes a first conductive plate having a semiconductor chip mounted thereon, and a second conductive plate that overlaps the semiconductor chip and at least two sides of the first conductive plate. In some embodiments, the semiconductor chip includes a source electrode, a drain electrode, and a gate electrode, and the first conductive plate includes a first terminal electrically connected to the drain electrode and a second terminal electrically connected to the gate electrode; a third terminal on the second conductive plate is provided on the at least two sides and electrically connected to the source electrode.
    Type: Application
    Filed: August 28, 2014
    Publication date: September 17, 2015
    Inventor: Miwako SUZUKI
  • Patent number: 8723253
    Abstract: According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Ohta, Masatoshi Arai, Miwako Suzuki
  • Publication number: 20140103427
    Abstract: According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).
    Type: Application
    Filed: December 26, 2013
    Publication date: April 17, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Miwako SUZUKI, Norio YASUHARA
  • Patent number: 8643095
    Abstract: According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miwako Suzuki, Norio Yasuhara
  • Patent number: 8629526
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Ohta, Masatoshi Arai, Miwako Suzuki
  • Patent number: 8552476
    Abstract: A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Ohta, Masatoshi Arai, Miwako Suzuki
  • Publication number: 20120241854
    Abstract: According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.
    Type: Application
    Filed: September 21, 2011
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi OHTA, Masatoshi Arai, Miwako Suzuki
  • Publication number: 20120241896
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.
    Type: Application
    Filed: September 15, 2011
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi OHTA, Masatoshi ARAI, Miwako SUZUKI
  • Publication number: 20120241853
    Abstract: A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.
    Type: Application
    Filed: September 19, 2011
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi OHTA, Masatoshi Arai, Miwako Suzuki
  • Publication number: 20120241898
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of the first conductivity type and a second electrode. The first semiconductor region includes a first portion including a first major surface and a second portion extending in a first direction perpendicular to the first major surface on the first major surface. The first electrode includes a third portion provided to face the second portion and is provided to be separated from the first semiconductor region. The second semiconductor region is provided between the second and third portions, includes a first concentration region having a lower impurity concentration than the first semiconductor region and forms a Schottky junction with the third portion. The second electrode is provided on an opposite side of the first major surface and in conduction with the first portion.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Ohta, Masatoshi Arai, Miwako Suzuki, Tadashi Matsuda
  • Publication number: 20120241851
    Abstract: According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).
    Type: Application
    Filed: September 21, 2011
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Miwako Suzuki, Norio Yasuhara