Patents by Inventor Mizuhisa Nihei

Mizuhisa Nihei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180179429
    Abstract: A thermal interface material, a method for preparing a thermal interface material, a thermally conductive pad, and a heat dissipation system are provided. In one example, the thermal interface material includes a metal zirconium coil and carbon nanotube arrays, where the metal zirconium coil has a first surface and a second surface that is opposite to the first surface. The carbon nanotubes in the carbon nanotube arrays are distributed on the first surface and the second surface. Further, the first surface and the second surface of the metal zirconium coil include exposed metal zirconium. Therefore, interface thermal resistance of the thermal interface material is reduced, and a heat conducting property of the thermal interface material is improved.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 28, 2018
    Inventors: Mizuhisa NIHEI, Xiaosong ZHOU, Keishin OTA
  • Patent number: 9991187
    Abstract: A semiconductor device includes: a silicon substrate that includes a heat release mechanism formed on a rear surface thereof; and an element layer that includes a transistor element and is formed on a front surface of the silicon substrate, the heat release mechanism including: a carbon material being a high heat-conducting material such as a CNT that is higher in heat conductivity than the silicon substrate and is formed in a plurality of first holes formed in the rear surface of the silicon substrate; and a carbon material being a heat-conductive film such as a multilayer graphene film that is thermally connected to the CNT in a manner to cover a rear surface side of the silicon substrate. This configuration provides a carbon material-embedded silicon substrate realizing very efficient heat release with a relatively simple configuration to obtain a highly-reliable electronic device.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 5, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Motonobu Sato, Mizuhisa Nihei
  • Patent number: 9576907
    Abstract: A wiring structure is made up by electrically connecting a via part made up by forming CNTs in a via hole and a wiring part made up of multilayer graphene on an interlayer insulating film via a metal block such as Cu. In the wiring structure using the CNTs at the via part and the graphene at the wiring part, it is thereby possible to obtain the wiring structure with high reliability enabling a certain electrical connection between the CNTs and the graphene with a relatively simple configuration.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: February 21, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shintaro Sato, Daiyu Kondo, Motonobu Sato, Mizuhisa Nihei
  • Publication number: 20150351285
    Abstract: A heat dissipation structure and a synthesizing method thereof are provided by the present disclosure. The method comprises: providing a metal foil; forming a deposition substrate on a first surface of the metal foil, wherein the deposition substrate includes a barrier layer disposed on the metal foil and a catalyst layer disposed on the barrier layer, such that catalyst in the catalyst layer is prevented from diffusing into the metal foil; and synthesizing a carbon nanotube array on the deposition substrate formed on the first surface. The method provided by the present disclosure can increase density of the CNTs in the heat dissipation structure.
    Type: Application
    Filed: February 3, 2015
    Publication date: December 3, 2015
    Inventors: Suguru NODA, Nuri NA, Mizuhisa NIHEI
  • Publication number: 20150325495
    Abstract: A semiconductor device includes: a silicon substrate that includes a heat release mechanism formed on a rear surface thereof; and an element layer that includes a transistor element and is formed on a front surface of the silicon substrate, the heat release mechanism including: a carbon material being a high heat-conducting material such as a CNT that is higher in heat conductivity than the silicon substrate and is formed in a plurality of first holes formed in the rear surface of the silicon substrate; and a carbon material being a heat-conductive film such as a multilayer graphene film that is thermally connected to the CNT in a manner to cover a rear surface side of the silicon substrate. This configuration provides a carbon material-embedded silicon substrate realizing very efficient heat release with a relatively simple configuration to obtain a highly-reliable electronic device.
    Type: Application
    Filed: July 17, 2015
    Publication date: November 12, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Motonobu SATO, Mizuhisa NIHEI
  • Publication number: 20150235960
    Abstract: A wiring structure is made up by electrically connecting a via part made up by forming CNTs in a via hole and a wiring part made up of multilayer graphene on an interlayer insulating film via a metal block such as Cu. In the wiring structure using the CNTs at the via part and the graphene at the wiring part, it is thereby possible to obtain the wiring structure with high reliability enabling a certain electrical connection between the CNTs and the graphene with a relatively simple configuration.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shintaro SATO, Daiyu KONDO, Motonobu SATO, Mizuhisa NIHEI
  • Patent number: 8533945
    Abstract: A CNT bundle is formed by growing a plurality of CNTs from opposing surfaces of contact blocks toward mutual opposing surfaces, and by contacting the CNTs so that they intersect to electrically connect with each other. Subsequently, a gap of the electrically connected CNT bundle is filled with a metal material, to thereby form a wiring being a composite state of the CNT bundle and the metal material.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: September 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Mizuhisa Nihei, Shintaro Sato, Daiyu Kondo, Yuji Awano
  • Patent number: 8372487
    Abstract: After forming an opening, a resist film is formed on the entire surface and a resist pattern is formed by patterning the resist film. The shape of the resist pattern is such that it covers one side of the bottom of the opening. As a result, a Si substrate is exposed only in one part of the opening. Then, using the resist pattern as a mask, a catalytic layer is formed on the bottom of the opening. Then, the resist pattern is removed. Carbon nanotubes are grown on the catalytic layer. At this time, since the catalytic layer is formed on only one side of the bottom of the opening, the Van der Waals force biased towards that side works horizontally on the growing carbon nanotubes. Therefore, the carbon nanotubes are attracted towards the nearest side of the SiO2 film and grow biased towards that side.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: February 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Akio Kawabata, Mizuhisa Nihei, Daiyu Kondo, Shintaro Sato
  • Patent number: 8163647
    Abstract: An electronic device having a structure of an ohmic connection to a carbon element cylindrical structure body, wherein a metal material is positioned inside the junction part of a carbon element cylindrical structure body joined to a connection objective and the carbon element cylindrical structure body and the connection objective are connected by an ohmic contact. Methods for producing such an electronic device are also disclosed. Further, a method for growing a carbon nanotube is disclosed.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Limited
    Inventors: Akio Kawabata, Mizuhisa Nihei
  • Patent number: 8029760
    Abstract: According to a method of manufacturing carbon nanotubes, minute concavities and convexities are formed at a surface of a substrate, a catalyst metal layer having a predetermined film thickness is formed on the surface having the concavities and convexities, the substrate is subject to a heat treatment at a predetermined temperature to change the catalyst metal layer into a plurality of isolated fine particles. The catalyst metal fine particles have a uniform particle diameter and uniform distribution. Then, the substrate supporting the plurality of fine particles is placed in a carbon-containing gas atmosphere to grow carbon nanotubes on the catalyst metal fine particles by a CVD method using the carbon-containing gas. The carbon nanotubes can be formed to have a desired diameter and a desired shell number with superior reproducibility.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Limited
    Inventors: Daiyu Kondo, Akio Kawabata, Shintaro Sato, Taisuke Iwai, Mizuhisa Nihei
  • Patent number: 7960277
    Abstract: An electronic device includes a conductive pattern formed on a first insulating film, a second insulating film formed on the conductive pattern and the first insulating film, a hole formed in the second insulating film on the conductive pattern, carbon nanotubes formed in the hole to extend from a surface of the conductive pattern, and a buried film buried in clearances among the carbon nanotubes in the hole.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 14, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mizuhisa Nihei
  • Patent number: 7948081
    Abstract: A semiconductor device uses a carbon nanotube structure, which reduces an electric resistance and a thermal resistance by increasing a density of the carbon nanotubes. An insulation film covers a first electrically conductive material. A second electrically conductive material is provided on the insulation film. A plurality of carbon nanotubes extend through the insulation film by being filled in an opening part that exposes the first electrically conductive material. The carbon nanotubes electrically connect the first electrically conductive material and the second electrically conductive material to each other. Ends of the carbon nanotubes are fixed to a recessed part provided on a surface of the first electrically conductive material.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: May 24, 2011
    Assignee: Fujitsu Limited
    Inventors: Akio Kawabata, Mizuhisa Nihei, Masahiro Horibe
  • Publication number: 20110073833
    Abstract: A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.
    Type: Application
    Filed: December 6, 2010
    Publication date: March 31, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Mizuhisa NIHEI, Hiroyasu Kawano
  • Patent number: 7883968
    Abstract: The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the channel current with a low voltage, and a method for simply and efficiently manufacturing such a field effect transistor not through a complex process such as a microfabrication process.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Limited
    Inventor: Mizuhisa Nihei
  • Patent number: 7867814
    Abstract: A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: January 11, 2011
    Assignee: Fujitsu Limited
    Inventors: Mizuhisa Nihei, Hiroyasu Kawano
  • Patent number: 7786487
    Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: August 31, 2010
    Assignee: Fujitsu Limited
    Inventors: Mizuhisa Nihei, Masahiro Horibe, Yuji Awano, Kazukiyo Joshin
  • Publication number: 20100151662
    Abstract: The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the channel current with a low voltage, and a method for simply and efficiently manufacturing such a field effect transistor not through a complex process such as a microfabrication process.
    Type: Application
    Filed: February 19, 2010
    Publication date: June 17, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Mizuhisa Nihei
  • Patent number: 7692238
    Abstract: The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the channel current with a low voltage, and a method for simply and efficiently manufacturing such a field effect transistor not through a complex process such as a microfabrication process.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: April 6, 2010
    Assignee: Fujitsu Limited
    Inventor: Mizuhisa Nihei
  • Publication number: 20090291216
    Abstract: After forming an opening, a resist film is formed on the entire surface and a resist pattern is formed by patterning the resist film. The shape of the resist pattern is such that it covers one side of the bottom of the opening. As a result, a Si substrate is exposed only in one part of the opening. Then, using the resist pattern as a mask, a catalytic layer is formed on the bottom of the opening. Then, the resist pattern is removed. Carbon nanotubes are grown on the catalytic layer. At this time, since the catalytic layer is formed on only one side of the bottom of the opening, the Van der Waals force biased towards that side works horizontally on the growing carbon nanotubes. Therefore, the carbon nanotubes are attracted towards the nearest side of the SiO2 film and grow biased towards that side.
    Type: Application
    Filed: June 4, 2009
    Publication date: November 26, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Akio Kawabata, Mizuhisa Nihei, Daiyu Kondo, Shintaro Sato
  • Publication number: 20090269921
    Abstract: An electronic device having a structure of an ohmic connection to a carbon element cylindrical structure body, wherein a metal material is positioned inside the junction part of a carbon element cylindrical structure body joined to a connection objective and the carbon element cylindrical structure body and the connection objective are connected by an ohmic contact. Methods for producing such an electronic device are also disclosed. Further, a method for growing a carbon nanotube is disclosed.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 29, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Akio Kawabata, Mizuhisa Nihei