Patents by Inventor Mizuhisa Nihei

Mizuhisa Nihei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020195618
    Abstract: A gate electrode rectangular in section is formed by patterning on a GaAs substrate as a compound substrate having a channel layer. Subsequently, a specific metal, e.g., Ti is deposited. A solid-phase reaction layer to serve as source/drain is formed in a self-alignment manner with the gate electrode by a thermal treatment. The part of the Ti film which has not been reacted is then removed. Thus the source/drain (or at least one of them) are very easily formed to a shallow junction depth without using any ion implantation process. Realized is a semiconductor device showing an excellent device characteristics, capable of suppressing occurrence of short-channel effect even in its shortened gate length for reducing the device size.
    Type: Application
    Filed: August 13, 2002
    Publication date: December 26, 2002
    Applicant: Fujitsu Limited
    Inventors: Mizuhisa Nihei, Yuu Watanabe
  • Publication number: 20020163012
    Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.
    Type: Application
    Filed: December 26, 2000
    Publication date: November 7, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Mizuhisa Nihei, Yuu Watanabe
  • Patent number: 6455361
    Abstract: A gate electrode rectangular in section is formed by patterning on a GaAs substrate as a compound substrate having a channel layer. Subsequently, a specific metal, e.g., Ti is deposited. A solid-phase reaction layer to serve as source/drain is formed in a self-alignment manner with the gate electrode by a thermal treatment. The part of the Ti film which has not been reacted is then removed. Thus the source/drain (or at least one of them) are very easily formed to a shallow junction depth without using any ion implantation process. Realized is a semiconductor device showing an excellent device characteristics, capable of suppressing occurrence of short-channel effect even in its shortened gate length for reducing the device size.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: September 24, 2002
    Assignee: Fujitsu Limited
    Inventors: Mizuhisa Nihei, Yuu Watanabe