Abstract: An array of photon counting phototoreceivers is constructed as an imager with micro-digitized pixels. Each photoreciever comprises a vertical cavity optical amplifier (VCSOA) as an optical amplifier, an avalanche photodiode as detector and an analog-to-digital converter (ADC) in an integrated structure. The ADC serves as a 1-bit digitizer and uses a resonant tunneling bipolar transistor RTBT. While the preferred embodiment of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made to the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of the present invention.

Abstract: A vertical cavity semiconductor optical photoamplifer (VCSOA) is used as a modulating retro-reflector (MRR) as a pixel in an array. The boundary of the cavity in the VCSOA forms a mirror for reflecting an incident light as an amplified output.

Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.

Abstract: A varactor has a plurality of alternating P? wells and N+ regions formed in a silicon layer. Each of the P? wells forms a first N+/P? junction with the N+ region on one of its side and a second N+/P? junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P? wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Abstract: A varactor having a capacitance includes a depletion mode transistor having a gate, a source, and a drain and an enhancement mode transistor also having a gate, a source, and a drain. The gates of the depletion mode transistor and the enhancement mode transistor are coupled together, the sources of the depletion mode transistor and the enhancement mode transistor are coupled together, and the drains of the depletion mode transistor and the enhancement mode transistor are coupled together. The enhancement mode transistor has a p/n junction. A bias source is coupled to the gates and the sources and drains so as to control the capacitance.

Abstract: One or more electrically conducting vias are formed through a silicon substrate having a first surface, an opposite second surface, and a thickness between the first and second surfaces. A conductive metallic material is deposited on the first surface of the silicon substrate. For example, the metallic material may be deposited at one or more depressions in the first surface at one or more desired via locations. The conductive metallic material is migrated through the silicon substrate from the first surface to the second surface. For example, the conductive metallic material may be thermally migrated, and an oxide layer at the second surface may by used to terminate the migration.

Abstract: A transistor has a first silicon layer comprising a source region and a drain region separated by a channel region. A gate oxide is formed over the first silicon layer. A second silicon layer is formed over the gate oxide and comprises a dual work function gate. The dual work function gate may include p+ and n+ gate regions such that the transistor has different threshold voltages.

Abstract: An RF semiconductor device is fabricated from a starting substrate comprising a polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the oxide layer.

Abstract: An RF semiconductor device is fabricated from a starting substrate comprising a polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the oxide layer.

Abstract: An RF semiconductor device is fabricated from a starting substrate comprising a polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the oxide layer.

Abstract: A method comprising etching a material under plasma etching conditions using an etching composition which has a GWP of no greater than about 3000 and which comprises at least one etchant compound having a formula selected from the group consisting of F—CO—[(CR1R2)m—CO]n—F and F—CO—R3—CO—F, and wherein: m=0, 1, 2, 3, 4, or 5; n=1; R1 & R2 represent H, F or CxHyFz; wherein: x=1 or 2; and y+z=2x+1; R3 represents CR4═CR5, R6R7C═C or C≡C; wherein: R4-7 represent H, F, or CxHyFz; wherein: x=1 or 2; and y+z=2x+1; and also including the cleaning of a surface by use of an etchant compound, and further including an etching composition which includes said etchant compound and also an etchant-modifier.

Abstract: A varactor has a plurality of alternating P− wells and N+ regions formed in a silicon layer. Each of the P− wells forms a first N+/P− junction with the N+ region on one of its side and a second N+/P− junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P− wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Abstract: A method of etching comprising subjecting a material under plasma etching conditions to an etching composition comprising at least an etchant compound having the formula CXHCFZ wherein: x=3, 4 or 5; 2x≧z≧y; and y+z=2x+2; and further including an etching composition which includes said etchant compound and a second material different from the etchant compound that enhances or modifies plasma etching.

Abstract: A method comprising etching a material under plasma etching conditions using an etching composition which has a GWP of no greater than about 3000 and which comprises at least one etchant compound having a formula selected from the group consisting of F—CO—[(CR1R2)m—CO]n−F and F—CO—R3—CO—F, and wherein:

Abstract: A method of etching comprising subjecting a material under plasma etching conditions to an etching composition comprising at least an etchant compound having the formula C.sub.X H.sub.C F.sub.Zwherein: x=3, 4 or 5;2x.gtoreq.z.gtoreq.y;and y+z=2x+2; andfurther including an etching composition which includes said etchant compound and a second material different from the etchant compound that enhances or modifies plasma etching.

Abstract: InP is etched by reactive ion etching using a mixture of SiCl.sub.4 and CH.sub.4 or a mixture of SiCl.sub.4 and H.sub.2. A mask is placed on the InP and then it is placed into a RIE chamber having a pressure between approximately 5 mTorr and approximately 50 mTorr. The InP substrate is etched at a substrate temperature of less than 150.degree. C.

Abstract: A two dimensional distributed amplifier phase shifter having a distributed reference amplifier circuit generating a reference signal, the reference amplifier circuit having its input connected to one end of a plurality of serially connected microstrip transmission lines. The phase shifter further has a plurality of phase shifted amplifier circuits, one associated with each of the microstrip transmission lines. Each phase shifted amplifier circuit has an input connected to an end of its associated microstrip transmission line which is opposite the reference amplifier circuit and generates an output signal, phase shifted from the reference signal or the output signal of an adjacent phase shifted amplifier by a predetermined phase angle. The phase shifter may be fabricated as a monolithic microwave integrated circuit.

Abstract: A method for forming a submicron width metal line on a substrate is described incorporating the steps of coating a substrate with a layer of photoresist, baking the layer, exposing the layer to a pattern, soaking the layer in a solution including chlorobenzene, developing the layer to form openings, baking the photoresist to remove any residual chlorobenzene, exposing the layer to deep ultraviolet radiation, baking the layer to cause the layer to flow at the edges of the openings, depositing metal on the layer and on the substrate, and dissolving the layer to lift off the metal disposited on the layer whereby the metal deposited on the substrate remains. The invention overcomes the problem of forming submicron width metal lines from one micron openings in a photoresist layer.

Abstract: A monolithic programmable signal processor with piezoelectric insulator FETs and an InP substrate. The piezoelectric insulator FETs are capable of being constructed on the same substrate with circuits associated with the signal processor and optical components.