Patents by Inventor Mokuji Kageyama
Mokuji Kageyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160071726Abstract: A method of manufacturing a semiconductor device includes forming a resist pattern on a first film to be processed by using photolithography, forming a dummy pattern on the first film by using a three-dimensional modeling machine, such as a three-dimensional printer. The dummy pattern is provided on a region of the first film that is not occupied by the resist pattern. The first film is then etched using the resist pattern and the dummy pattern as a mask. A second film is then formed on the etched first film and subsequently flattened/planarized using, for example, chemical mechanical polishing.Type: ApplicationFiled: February 17, 2015Publication date: March 10, 2016Inventors: Hiroshi MIZUNO, Takeshi SUNADA, Mokuji KAGEYAMA, Tadashi MATSUNO
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Publication number: 20160027833Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first plane and a second plane facing the first plane. A semiconductor element is formed in the semiconductor layer. The semiconductor layer includes a separation region formed to extend from the first plane to the second plane. The separation region surrounds a region where the semiconductor element is formed. The separation region includes a first separation region formed from the first plane of the semiconductor layer toward an interior of the semiconductor layer, and a second separation region formed from the second plane of the semiconductor layer to the first separation region.Type: ApplicationFiled: March 6, 2015Publication date: January 28, 2016Inventors: Masaaki Yamamoto, Kentaro Imamizu, Mokuji Kageyama
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Publication number: 20150263212Abstract: According to one embodiment, a substrate for semiconductor devices includes a P-type semiconductor substrate, a P-type or N-type semiconductor layer, and a P-type or N-type epitaxial layer. The P-type or N-type semiconductor layer is provided at a surface layer of the semiconductor substrate and has a resistance value lower than a resistance value of the semiconductor substrate. The P-type or N-type epitaxial layer is provided on a surface of the semiconductor layer and has a resistance value higher than the resistance value of the semiconductor layer.Type: ApplicationFiled: March 2, 2015Publication date: September 17, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shinji UYA, Nagataka Tanaka, Mokuji Kageyama, Hideo Numata
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Publication number: 20150221593Abstract: According to one embodiment, in a semiconductor device, a plurality of first wiring lines is provided in a first insulating film on a semiconductor substrate and is adjacent in a direction parallel to the semiconductor substrate. A second insulating film is provided on the first wiring lines and the first insulating film. A plurality of vias is provided in the second insulating film and is electrically connected to the first wiring lines. A third insulating film is provided on the vias and the second insulating film. Adjacent second wiring lines are provided in the third insulating film and are electrically connected to the vias. A fourth insulating film is provided on a sidewall of each of the adjacent second wiring lines, the sidewalls face each other. A conductive film abuts on the adjacent second wiring lines with the fourth insulating film interposed therebetween.Type: ApplicationFiled: November 14, 2014Publication date: August 6, 2015Inventors: Masaaki YAMAMOTO, Takeshi SUNADA, Mokuji KAGEYAMA, Kazuhiro TAKIMOTO
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Patent number: 6274505Abstract: By locally heating or cooling a substrate in an etching process, temperature unevenness is controlled, and convection currents of an etching liquid are restricted simultaneously. By setting the etching temperature low in an initial stage of the etching process and increasing it in a final stage, uniform and quick etching is possible. In a drop etching method, generation of bubbles can be prevented to ensure uniform etching by providing gas release openings in a member opposed to the substrate.Type: GrantFiled: September 1, 1999Date of Patent: August 14, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Shoko Ito, Mokuji Kageyama
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Patent number: 6165872Abstract: A denuded zone DZ least liable to generate defects is formed in a surface layer zone 12 of a semiconductor wafer 10. In an inner layer zone 18 of the semiconductor wafer 10, micro defects BMD for gettering of impurity metal are made. In the inner layer zone 18, the precipitation of oxygen decreases with the depth. As a result, mechanical strength can be maintained while improving the gettering performance of impurity metal.Type: GrantFiled: May 28, 1999Date of Patent: December 26, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Mokuji Kageyama
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Patent number: 6037270Abstract: The gate oxide film is prevented from being thinned partially. The semiconductor substrate (wafer) can be etched (processed) under excellent conditions. The impurities on the wafer surface can be analyzed and further reduced. In the first aspect, the substrate is irradiated with ultraviolet rays in contact with an F-containing aqueous solution, so that the oxide film and the substrate can be etched at roughly the same etching speed under excellent controllability without deteriorating the planarization of the substrate. In the second aspect, the substrate is etched by irradiating ultraviolet rays during exposure to an acid aqueous solution, so that surface metallic contamination and particles can be removed without deteriorating the wafer surface roughness. Further, the impurity elements in the outermost surface layer of the wafer can be analyzed at high precision by analyzing elements contained in the acid aqueous solution used for the etching.Type: GrantFiled: June 29, 1995Date of Patent: March 14, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Mokuji Kageyama, Moriya Miyashita
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Patent number: 5939770Abstract: A denuded zone DZ least liable to generate defects is formed in a surface layer zone 12 of a semiconductor wafer 10. In an inner layer zone 18 of the semiconductor wafer 10, micro defects BMD for gettering of impurity metal are made. In the inner layer zone 18, the precipitation of oxygen decreases with the depth. As a result, mechanical strength can be maintained while improving the gettering performance of impurity metal.Type: GrantFiled: August 28, 1998Date of Patent: August 17, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Mokuji Kageyama
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Patent number: 5574307Abstract: A semiconductor apparatus has a silicon substrate sliced off from a silicon ingot produced by the pulling method or floating zone method, wherein the concentration of interstitial oxygen in a region with a depth of approximately 10 .mu.m or less from a device forming surface is minimum except for the device forming surface. According to the present invention, in the semiconductor apparatus production process, in the inner region with a depth of approximately 10 .mu.m from the device forming surface of the silicon substrate, the inner region affecting the device operation, oxygen does not precipitate. Moreover, in a more inner region, oxygen precipitates, thereby providing a gettering effect with respect to metal impurities.Type: GrantFiled: December 16, 1994Date of Patent: November 12, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Mokuji Kageyama, Yoshiaki Matsushita
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Patent number: 5395446Abstract: A semiconductor treatment apparatus has a gas-phase decomposing device for decomposing a gas-phase on a surface of a semiconductor substrate, a substrate supporting device for supporting the substrate, and a substrate transfer device for transferring the substrate between the gas-phase decomposing device and the substrate supporting device. The apparatus further has a liquid-drop applicator for applying a liquid-drop on the surface of the substrate supported by the substrate supporting device, with the liquid-drop being brought into contact with the surface of the substrate, and a liquid-drop preserving device for preserving the liquid-drop that has been applied to the surface of the substrate.Type: GrantFiled: December 3, 1993Date of Patent: March 7, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Mokuji Kageyama, Kiyoshi Yoshikawa, Ayako Shimazaki
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Patent number: 5271796Abstract: A method of detecting a defect on the surface of a semiconductor substrate, including: a first etching step of etching a semiconductor substrate by a first etching amount; a first check step of applying a beam to the surface of the substrate underwent the first etching step, and detecting a first reflected beam; a second etching step of etching the substrate etched by the first etching amount, by an additional etching amount, to make the total etching amount a second etching amount; a second check step of applying the beam to the surface of the substrate underwent the second etching step, and detecting a second reflected beam; and a calculation step of calculating the relation between the first and second reflected beams.Type: GrantFiled: March 27, 1992Date of Patent: December 21, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Moriya Miyashita, Mokuji Kageyama, Hachiro Hiratsuka
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Patent number: 5148457Abstract: A system for analyzing a metal impurity at the surface of a single crystal semiconductor comprising: an incident device for allowing X-ray to be incident, at an incident angle less than a total reflection angle, onto the surface of a wafer in the form of a thin plate comprised of a single crystal semiconductor (e.g., silicon); a wafer fixing/positioning stage wherein when it is assumed that the wafer surface is partitioned by a lattice having an interval d, and that the wavelength of the X-ray from the incident device is .lambda., an angle that the X-ray and the wafer surface form is .theta., and an arbitrary integer is n, the stage is adapted to fix the crystal orientation of the wafer so as to satisfy the condition of "2d sin .theta..noteq.n.lambda.Type: GrantFiled: June 27, 1991Date of Patent: September 15, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Kubota, Norihiko Tsuchiya, Shuichi Samata, Yoshiaki Matsushita, Mokuji Kageyama
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Patent number: 5055413Abstract: An object to be measured is moved relative to a stick prepared by cooling and solidifying a solution into a rod-like shape. The stick is brought into contact with the surface of the object to be measured, thereby dissolving a natural oxide film and the like formed on the surface of the object. After the stick is brought into contact with the overall surface of the object to be measured, the solution held at the end portion of the stick is analyzed by chemical analysis to measure the type and amount of an impurity adhered on the surface of the object.Type: GrantFiled: April 17, 1989Date of Patent: October 8, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Mokuji Kageyama, Ayako Maeda
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Patent number: 4990459Abstract: A drop which is hydrophobic to the surface of an object to be measured is dropped on the surface of the object and moved so as to be brought into contact with the overall surface of the object to be measured. After the movement, the drop is recovered and analyzed by chemical analysis to measure the kind of element and content of an impurity adsorbed on the surface of the object to be measured.Type: GrantFiled: April 18, 1989Date of Patent: February 5, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Ayako Maeda, Mokuji Kageyama, Shintaro Yoshii, Masanobu Ogino