Patents by Inventor Moon-kyung Kim

Moon-kyung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10298197
    Abstract: A bulk acoustic wave resonator includes: a substrate; a cavity forming layer disposed on the substrate so as to form a cavity; a lower electrode disposed on the cavity; a piezoelectric layer disposed on the lower electrode; an upper electrode disposed on the piezoelectric layer; and a temperature compensation layer disposed below the lower electrode and in the cavity portion.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Moon Chul Lee, Jae Chang Lee, Chang Hyun Lim, Tae Hun Lee, Tae Kyung Lee, Tae Yoon Kim
  • Patent number: 10298201
    Abstract: A bulk acoustic wave resonator may include: an air cavity; an etching stop layer and an etching stop part, which define a lower boundary surface and a side boundary surface of the air cavity; and a resonating part formed on an approximately planar surface, which is formed by a upper boundary surface of the air cavity and a top surface of the etching stop part. A width of a top surface of the etching stop part may be greater than a width of a bottom surface of the etching stop part. A side surface of the etching stop part connecting the top surface of the etching stop part to the bottom surface of the etching stop part may be inclined.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Yoon Kim, Tae Kyung Lee, Moon Chul Lee, Sung Min Cho, Sang Kee Yoon
  • Publication number: 20190065711
    Abstract: An electronic device is provided.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 28, 2019
    Inventors: Dong-Wook Seo, Seong-Hun Moon, Moon-Kyung Kim, Myeong-Jin Oh, Se-Yeong Lee, Da-Som Lee
  • Publication number: 20170115981
    Abstract: A method for application management and an electronic device therefor are provided. The electronic device includes a memory configured to store a first application, and a processor configured to obtain a request for installing a second application, compare a first identifier corresponding to the first application with a second identifier corresponding to the second application, if the first identifier is the same as the second identifier, compare first signature information corresponding to the first application with second signature information corresponding to the second application, if the first signature information is different from the second signature information, compare the first signature information with additional signature information corresponding to the second application, and if the first signature information is the same as the additional signature information, replace at least a portion of the first application by using at least a portion of the second application.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 27, 2017
    Inventors: Myeong Jin OH, Moon Kyung KIM, Kyung Moon KIM, Jae Young LEE
  • Publication number: 20160232365
    Abstract: Disclosed is an electronic device including a memory configured to store inheritance limitation information of sharing permission owned by an application in a sharing permission relationship with an installed or executed application for sharing at least part of permission, and a processor functionally connected to the memory and set to process a sharing permission acquisition of the installed or executed application, based on the inheritance limitation information of the sharing permission when the application is installed or executed.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 11, 2016
    Inventors: Myeong Jin OH, Moon Kyung KIM
  • Patent number: 8843854
    Abstract: A method for executing a menu in a mobile terminal is disclosed, wherein the method includes displaying a first icon on a touch screen of the mobile terminal, receiving a first multi touch gesture pattern on the first icon, and displaying at least one second icon upon recognition of the first multi-gesture pattern, the at least one second icon a sub icon of the first icon.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: September 23, 2014
    Assignee: LG Electronics Inc.
    Inventors: Se Sook Oh, Ho Jae Jung, Moon Kyung Kim
  • Patent number: 8080839
    Abstract: An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Sandip Tiwari, Moon-Kyung Kim, Joshua Mark Rubin, Soo-Doo Chae, Choong-Man Lee, Ravishankar Sundararaman
  • Publication number: 20110049650
    Abstract: An electromechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Inventors: Sandip Tiwari, Moon-Kyung Kim, Joshua Mark Rubin, Soo-Doo Chae, Choong-Man Lee, Ravishankar Sundararaman
  • Publication number: 20100299635
    Abstract: A method for executing a menu in a mobile terminal is disclosed, wherein the method includes displaying a first icon on a touch screen of the mobile terminal, receiving a first multi touch gesture pattern on the first icon, and displaying at least one second icon upon recognition of the first multi-gesture pattern, the at least one second icon a sub icon of the first icon.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 25, 2010
    Inventors: Se Sook Oh, Ho Jae Jung, Moon Kyung Kim
  • Patent number: 7759196
    Abstract: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-doo Chae, Moon-kyung Kim, Jo-won Lee, Chung-woo Kim
  • Publication number: 20090068808
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 12, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-doo Chae, Chung-woo Kim, Jung-hyun Lee, Moon-kyung Kim, Hyun-sang Hwang
  • Publication number: 20090010058
    Abstract: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
    Type: Application
    Filed: September 12, 2008
    Publication date: January 8, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-doo CHAE, Moon-kyung Kim, Jo-won Lee, Chung-woo Kim
  • Patent number: 7432554
    Abstract: A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 7, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Kyung Kim, Jo-Won Lee, Yoon-Dong Park, Chung-Woo Kim
  • Patent number: 7426031
    Abstract: A defect inspecting apparatus includes a first support unit supporting a standard sample having standard defects, a second support unit supporting a wafer having target defects, a light source irradiating an incident light to the standard sample or the wafer, a light receiving part collecting reflection light reflected from the standard sample and the wafer, a detection part detecting the standard defects and the target defects by using the reflection light, a comparing part comparing information obtained using the reflection light reflected from the standard sample with a predetermined standard information of the standard defects to confirm a reliability of a step for detecting the target defects and a determination portion determining whether the step is allowed to be performed or not.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Kyung Kim, Chung-Sam Jun, Yu-Sin Yang
  • Patent number: 7420256
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-doo Chae, Chung-woo Kim, Jung-hyun Lee, Moon-kyung Kim, Hyun-sang Hwang
  • Patent number: 7310140
    Abstract: In a method and an apparatus for inspecting a wafer surface, a wafer is loaded into a chamber. An incident light including a first light for sensing a vertical position of the wafer and a second light for inspecting the wafer surface is irradiated onto the wafer. The first light is reflected on an inspection region or a next inspection region of the wafer and is detected to control a wafer position. The second light is scattered on the inspection region and is detected to inspect the wafer surface of the inspection region. Position information of a wafer is examined and a position of the wafer is adjusted before inspecting a surface of inspection region of a wafer so as to enable accurate inspection of the wafer surface.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: December 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Min Eom, Yu-Sin Yang, Chung-Sam Jun, Yun-Jung Jee, Joung-Soo Kim, Moon-Kyung Kim, Sang-Mun Chon, Sun-Yong Choi
  • Patent number: 7271890
    Abstract: In a method for inspecting a defect in accordance with one aspect of the present invention, an object is divided into a plurality of regions. Reflectivity of each of the plurality of regions is obtained. Amplification ratio for each region is determined using the reflectivity. A light is irradiated onto the regions. A light reflected from a first region is amplified by a first amplification ratio that is determined for the first region. Moving the irradiated light from the first region to a second region is detected. A light reflected from the second region is amplified by a second amplification ratio that is determined for the second region. The amplified lights from the first region and the second region are analyzed to determine an existence of a defect on the object.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: September 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joung-Soo Kim, Yu-Sin Yang, Moon-Kyung Kim, Sang-Mun Chon, Sun-Yong Choi, Chung-Sam Jun
  • Publication number: 20070138541
    Abstract: A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
    Type: Application
    Filed: February 5, 2007
    Publication date: June 21, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-doo Chae, Chung-woo Kim, Jo-won Lee, Moon-kyung Kim
  • Patent number: 7202521
    Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-kyung Kim, Chung-woo Kim, Jo-won Lee, Eun-hong Lee, Hee-soon Chae
  • Patent number: 7187030
    Abstract: A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: March 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-doo Chae, Chung-woo Kim, Jo-won Lee, Moon-kyung Kim