Abstract: A display device including: a display panel including a plurality of pixels; an input sensor disposed on the display panel and including detection electrodes; a data driving circuit configured to output data signals or detection driving signals; and a selection circuit configured to provide the data signals to the plurality of pixels in response to a first enable signal and provide the detection driving signals to the detection electrodes in response to a second enable signal.

Abstract: A communication system includes one or more communication apparatuses, each including a transmission circuit and a reception circuit. The transmission circuit includes a transmission unit and a signal generator. The transmission unit transmits one of a first transmission signal including first transmission data or a second transmission signal including at least one of a periodic signal with a constant frequency or a narrow band modulation signal having lower speed than the first transmission data. The signal generator generates the second transmission signal. The reception circuit includes a reception unit that receives the first transmission signal and the second transmission signal a narrow band detector that outputs a narrow band detection signal through detecting the second transmission signal in a narrow band, and a determination unit that determines presence of a significant signal or presence of significant signal change in the narrow band detection signal and outputs a determination signal.

Abstract: A communication system of the present disclosure includes one or more communication apparatuses, each of which includes: a transmission circuit including a transmission unit and a signal generator, the transmission unit that selectively transmits, via an antenna unit, one of a first transmission signal including first transmission data or a second transmission signal including at least one of a periodic signal with a constant frequency or a narrow band modulation signal by data having lower speed than the first transmission data, and the signal generator that generates the second transmission signal; and a reception circuit including a reception unit, a narrow band detector, and a determination unit, the reception unit that receives the first transmission signal and the second transmission signal via the antenna unit, the narrow band detector that outputs a narrow band detection signal through detecting the second transmission signal in a narrow band, and the determination unit that determines presence or abs

Abstract: There is provided a power supply switching circuit including a first control signal output unit that outputs a signal exceeding a predetermined potential using a main power supply as a first control signal when a power supply voltage of the main power supply exceeds a predetermined reference voltage, a second control signal output unit that outputs the signal exceeding the predetermined potential using a standby power supply from a battery as a second control signal when a potential of the first control signal does not exceed the predetermined potential, and a power supply output unit that outputs the main power supply when the first control signal exceeds the predetermined potential and outputs the standby power supply when the second control signal exceeds the predetermined potential.

Abstract: There is provided a circuit including a capacitor, a current source configured to supply a current to the capacitor, a comparator configured to output a result of comparison between a voltage stored in the capacitor and a predetermined voltage, and a switch section configured to intermittently which is caused to flow to the capacitor by the current source.

Abstract: There is provided a voltage detector including a reference voltage generator that generates a constant reference voltage when a power supply voltage is higher than a predetermined threshold voltage, and a detector that, when the power supply voltage exceeds a voltage that is higher than the threshold voltage by a predetermined potential, detects whether the power supply voltage is higher than a defined voltage based on the reference voltage and outputs a detection result.

Abstract: There is provided a circuit including a capacitor, a current source configured to supply a current to the capacitor, a comparator configured to output a result of comparison between a voltage stored in the capacitor and a predetermined voltage, and a switch section configured to intermittently which is caused to flow to the capacitor by the current source.

Abstract: There is provided a power supply switching circuit including a first control signal output unit that outputs a signal exceeding a predetermined potential using a main power supply as a first control signal when a power supply voltage of the main power supply exceeds a predetermined reference voltage, a second control signal output unit that outputs the signal exceeding the predetermined potential using a standby power supply from a battery as a second control signal when a potential of the first control signal does not exceed the predetermined potential, and a power supply output unit that outputs the main power supply when the first control signal exceeds the predetermined potential and outputs the standby power supply when the second control signal exceeds the predetermined potential

Abstract: There is provided a voltage detector including a reference voltage generator that generates a constant reference voltage when a power supply voltage is higher than a predetermined threshold voltage, and a detector that, when the power supply voltage exceeds a voltage that is higher than the threshold voltage by a predetermined potential, detects whether the power supply voltage is higher than a defined voltage based on the reference voltage and outputs a detection result.

Abstract: A bandgap reference circuit includes: a first PMOSFET connected to a power supply node; a first resistor connected to a drain of the first PMOSFET; a first diode connected to the first resistor and a ground node; a second PMOSFET connected to the power supply node; a second diode connected to a drain of the second PMOSFET and the ground node; a second resistor connected between the first PMOSFET and ground node; a third resistor connected between the second PMOSFET and ground node; a third PMOSFET connected to the power supply node and an output node of a reference voltage; a fourth resistor connected between the third PMOSFET and ground node; and an operational amplifier having a non-inverting input terminal connected to the first PMOSFET and an inverting input terminal connected to the second PMOSFET, an output voltage being applied to each gate of the first to third PMOSFETs.

Abstract: In a sampling block 40a-1, an intermediate frequency signal RIFs is sampled at a frequency of the intermediate frequency signal RIFs multiplied by “1/(m+0.25)” or “1/(m+0.75)” (m: 0 or natural number), to generate signals having phase differences “0”, “?/2”, “?”, and “3?/2”. A polarity adjustment block 40a-2 matches a polarity of the signal having phase difference “?” with that of the signal having phase difference “0”. Further, it matches a polarity of the signal having phase difference “3?/2” with that of the signal having phase difference “?/2”. In a signal synthesis block 40a-3, the signal with phase difference “0” and the signal with phase difference “?” having phase difference “?” from each other are synthesized and held to be output as a demodulated signal PI. Further, the signal with phase difference “?/2” and the signal with phase difference “3?/2” having phase difference “?” from each other are synthesized and held to be output as a demodulated signal PQ.

Abstract: In a sampling block 40a-1, an intermediate frequency signal RIFs is sampled at a frequency of the intermediate frequency signal RIFs multiplied by “1/(m+0.25)” or “1/(m+0.75)” (m: 0 or natural number), to generate signals having phase differences “0”, “?/2”, “?”, and “3?/2”. A polarity adjustment block 40a-2 matches a polarity of the signal having phase difference “?” with that of the signal having phase difference “0”. Further, it matches a polarity of the signal having phase difference “3?/2” with that of the signal having phase difference “?/2”. In a signal synthesis block 40a-3, the signal with phase difference “?” and the signal with phase difference “?” having phase difference “?” from each other are synthesized and held to be output as a demodulated signal PI. Further, the signal with phase difference “?/2” and the signal with phase difference “3?/2” having phase difference “?” from each other are synthesized and held to be output as a demodulated signal PQ.