Patents by Inventor Morihiko Ikemizu
Morihiko Ikemizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10840166Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip, a heat dissipation member provided on one surface of the first semiconductor chip and connected to the first semiconductor chip, and a sealing resin sealing the first semiconductor chip and the heat dissipation member. The heat dissipation member includes mutually interlaced metal fibers and a thermosetting resin.Type: GrantFiled: September 12, 2018Date of Patent: November 17, 2020Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Kumiko Karouji, Morihiko Ikemizu, Yoshihisa Imori, Hiroaki Kishi, Tomohiko Imada, Akito Shimizu
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Publication number: 20190295923Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip, a heat dissipation member provided on one surface of the first semiconductor chip and connected to the first semiconductor chip, and a sealing resin sealing the first semiconductor chip and the heat dissipation member. The heat dissipation member includes mutually interlaced metal fibers and a thermosetting resin.Type: ApplicationFiled: September 12, 2018Publication date: September 26, 2019Inventors: Kumiko Karouji, Morihiko Ikemizu, Yoshihisa Imori, Hiroaki Kishi, Tomohiko Imada, Akito Shimizu
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Patent number: 6495922Abstract: Bumps each having a pointed tip end or grooves are formed on electrodes of a chip, and they pierce wiring layers of an insulating film substrate such as an interposer so as to tear an oxide film or a contaminated layer produced on the surface of each of wiring layers. A new interface of the material is enabled to be continuously produced between the bumps and the wiring layers, thus making it possible to obtain an excellent electrical connection among them.Type: GrantFiled: March 13, 2001Date of Patent: December 17, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Yokoi, Morihiko Ikemizu
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Publication number: 20020011677Abstract: gBumps each having a pointed tip end or grooves are formed on electrodes of a chip, and they pierce wiring layers of an insulating film substrate such as an interposer so as to tear an oxide film or a contaminated layer produced on the surface of each of wiring layers. A new interface of the material is enabled to be continuously produced between the bumps and the wiring layers, thus making it possible to obtain an excellent electrical connection among them.Type: ApplicationFiled: March 13, 2001Publication date: January 31, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuya Yokoi, Morihiko Ikemizu
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Patent number: 6326243Abstract: A semiconductor chip having a plurality of electrodes on its surface is fixed onto a die pad. The leads are spaced away from the die pad and connected to the electrodes of the semiconductor chip by means of a TAB tape. The die pad is substantially equal in size to the insulation film of the TAB tape. The die pad has a plurality of resin circulating holes around the semiconductor chip. The resin circulating holes are arranged such that a fluid resin sufficiently flows into a narrow area between the TAB tape and die pad. On the die pad, portions each between adjacent resin circulating holes serves as heat conducting paths. The heat generated from the semiconductor chip is transmitted to the entire region of the die pad through the heat conducting paths and then radiated outside.Type: GrantFiled: December 31, 1997Date of Patent: December 4, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhito Suzuya, Morihiko Ikemizu, Terunari Takano, Kenji Uehara, Akito Yoshida
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Patent number: 6097085Abstract: The electronic device has a structure that a semiconductor package is mounted on a mother board. To relieve stress caused by cyclic thermal load and applied to solder bumps that are electrically and mechanically connect the semiconductor package and the mother board, a shape-holding plate (stiffener) adhered to a wiring film is composed of a metal with a thermal expansion coefficient of 13.times.10.sup.-6 to 17.times.10.sup.-6 almost close to that of a glass-epoxy wiring substrate as the mother board. Examples of the metal are 25Cr-20Ni stainless steel or copper alloy containing 0.01 to 0.03% by weight of Zr.Type: GrantFiled: August 26, 1998Date of Patent: August 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Morihiko Ikemizu, Nobuaki Oie, Ken Iwasaki
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Patent number: 5892277Abstract: In a TAB tape, dummy copper foil patterns are provided on the portions of an adhesive on which neither pads nor leads are provided, thereby flattening the upper surface of solder resist coated on the resultant structure.Type: GrantFiled: June 19, 1997Date of Patent: April 6, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Morihiko Ikemizu, Takayuki Okutomo, Yutaka Fukuoka, Masafumi Takeuchi
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Patent number: 5753969Abstract: A semiconductor chip having a plurality of electrodes on its surface is fixed onto a die pad. The leads are spaced away from the die pad and connected to the electrodes of the semiconductor chip by means of a TAB tape. The die pad is substantially equal in size to the insulation film of the TAB tape. The die pad has a plurality of resin circulating holes around the semiconductor chip. The resin circulating holes are arranged such that a fluid resin sufficiently flows into a narrow area between the TAB tape and die pad. On the die pad, portions each between adjacent resin circulating holes serves as heat conducting paths. The heat generated from the semiconductor chip is transmitted to the entire region of the die pad through the heat conducting paths and then radiated outside.Type: GrantFiled: August 14, 1996Date of Patent: May 19, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhito Suzuya, Morihiko Ikemizu, Terunari Takano, Kenji Uehara, Akito Yoshida
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Patent number: 5659198Abstract: A wiring pattern having a plurality of leads is formed on the under surface of an insulating film. The inner lead portion of each of the leads is bonded to a corresponding one of bump electrodes formed on pads of a semiconductor chip and the outer lead portion thereof is connected to a corresponding lead wire formed on a printed circuit board. The outer lead portion of one of the leads which acts as a ground line is connected to a grounded lead wire which is formed on the printed circuit board. A shield plate is bonded to the under surface of the leads via insulating adhesive agent. The shield plate is electrically connected to the grounded lead wire. The semiconductor chip and the inner lead portions are hermetically sealed by use of potting resin.Type: GrantFiled: October 5, 1995Date of Patent: August 19, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Okutomo, Morihiko Ikemizu
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Patent number: 5652184Abstract: The present invention provides a semiconductor device. In the device of the present invention, a metal lead wire is mounted to one surface of a carrier tape. One end of the metal lead wire is connected to a semiconductor chip. A lead frame is mounted to one surface of a reinforcing plate. The other end of the metal lead wire is connected to one end of an inner lead wire. The semiconductor chip is mounted to one surface of the reinforcing plate having an open portion positioned in the tip portion of the inner lead. Further, the semiconductor chip is covered with a resin layer.Type: GrantFiled: May 4, 1995Date of Patent: July 29, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Masao Goto, Morihiko Ikemizu
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Patent number: 5612259Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, each of electrode pads on a semiconductor chip is bonded to an inner lead section of each of leads of a carrier tape by a connecting electrode. An insulating film of the carrier tape is then adhered to the surface of the semiconductor chip by interposing an adhesive layer between them. Thus, the electrode pads and inner lead sections are stably bonded, and the flatness of the carrier tape is maintained by the flatness of the surface of the semiconductor chip. It is thus possible to prevent the flatness of the outer lead sections of the leads from being degraded when the number of leads is small, and to improve in mounting the semiconductor chip by reflow soldering.Type: GrantFiled: July 16, 1995Date of Patent: March 18, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Okutomo, Morihiko Ikemizu
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Patent number: 5442232Abstract: The present invention provides a semiconductor device. In the device of the present invention, a metal lead wire is mounted to one surface of a carrier tape. One end of the metal lead wire is connected to a semiconductor chip. A lead frame is mounted to one surface of a reinforcing plate. The other end of the metal lead wire is connected to one end of an inner lead wire. The semiconductor chip is mounted to one surface of the reinforcing plate having an open portion positioned in the tip portion of the inner lead. Further, the semiconductor chip is covered with a resin layer.Type: GrantFiled: December 23, 1993Date of Patent: August 15, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Masao Goto, Morihiko Ikemizu
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Patent number: 5359222Abstract: A wiring pattern having a plurality of leads is formed on the under surface of an insulating film. The inner lead portion of each of the leads is bonded to a corresponding one of bump electrodes formed on pads of a semiconductor chip and the outer lead portion thereof is connected to a corresponding lead wire formed on a printed circuit board. The outer lead portion of one of the leads which acts as a ground line is connected to a grounded lead wire which is formed on the printed circuit board. A shield plate is bonded to the under surface of the leads via insulating adhesive agent. The shield plate is electrically connected to the grounded lead wire. The semiconductor chip and the inner lead portions are hermetically sealed by use of potting resin.Type: GrantFiled: January 29, 1993Date of Patent: October 25, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Okutomo, Morihiko Ikemizu