Patents by Inventor Morio Fujitani

Morio Fujitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140084778
    Abstract: A plasma display panel includes: a front plate including an image display area and an image non-display area provided outside the image display area; and a rear plate provided to be opposed to the front plate. The front plate has a substrate, and a display electrode provided over the substrate. The display electrode has, in the image display area, a stacked structure of a first electrode and a second electrode provided over the first electrode. Furthermore, the display electrode has, in at least a portion of the image non-display area, a first region and a second region provided around the first region. The first region has a single-layer structure of a second electrode. The second region has a stacked structure of a first electrode and the second electrode provided over the first electrode. The surface of the display electrode has a sparse degree between 12% and 15% (inclusive).
    Type: Application
    Filed: November 22, 2012
    Publication date: March 27, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Tomokiyo Yamada, Yasutaka Tsutsui, Taishi Asano, Kenta Hosoi, Morio Fujitani
  • Patent number: 8362680
    Abstract: In a plasma display panel, in which an area percentage of the display electrodes in an area of an image display region of the front panel is expressed by a longitudinal axis, and a difference between a coefficient of expansion of the front substrate from room temperature to 300° C. and a coefficient of expansion of the dielectric layer from room temperature to 300° C. is expressed by a lateral axis, the difference between the coefficients of expansion and the area percentage stay within a region formed by connecting coordinates (35×10?7/° C., 60%), coordinates (8×10?7/° C., 60%), coordinates (5×10?7/° C., 40%), and coordinates (23×10?7/° C., 40%) in the mentioned order with a straight line where the straight line is included.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: January 29, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Morioka, Morio Fujitani, Hirofumi Higashi, Shinsuke Yoshida, Akira Kawase, Tatsuo Mifune
  • Patent number: 8350474
    Abstract: A plasma display panel includes a front plate and a rear plate disposed in such a manner as to face the front plate. The front plate has a display electrode and a dielectric layer covering the display electrode. The dielectric layer contains substantially no lead components but contains MgO, SiO2, and K2O. A content of MgO is in a range between 0.3 mol % and 1.0 mol %, both inclusive. The content of SiO2 is in a range between 35 mol % and 50 mol %, both inclusive.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshiyuki Ota, Kazuhiro Morioka, Akira Kawase, Morio Fujitani, Tatsuo Mifune
  • Publication number: 20110285281
    Abstract: A plasma display panel includes a front plate and a rear plate disposed in such a manner as to face the front plate. The front plate has a display electrode and a dielectric layer covering the display electrode. The dielectric layer contains substantially no lead components but contains MgO, SiO2, and K2O. A content of MgO is in a range between 0.3 mol % and 1.0 mol %, both inclusive. The content of SiO2 is in a range between 35 mol % and 50 mol %, both inclusive.
    Type: Application
    Filed: December 17, 2010
    Publication date: November 24, 2011
    Inventors: Yoshiyuki Ota, Kazuhiro Morioka, Akira Kawase, Morio Fujitani, Tatsuo Mifune
  • Publication number: 20110169401
    Abstract: The PDP has front plate and a rear plate. Front plate and the rear plate are oppositely disposed and sealed at the peripheries. Front plate has display electrode and dielectric layer. Dielectric layer contains an oxide of a divalent element, an oxide of a trivalent element, and an oxide of a tetravalent element. The total content of the oxide of a trivalent element and the oxide of a tetravalent element is larger by weight than the content of the oxide of a divalent element.
    Type: Application
    Filed: June 23, 2010
    Publication date: July 14, 2011
    Inventors: Shinsuke Yoshida, Akira Kawase, Kazuhiro Morioka, Naoto Haze, Yoshiyuki Ota, Morio Fujitani, Hiroshi Ito, Tatsuo Mifune
  • Publication number: 20110062854
    Abstract: In a plasma display panel, in which an area percentage of the display electrodes in an area of an image display region of the front panel is expressed by a longitudinal axis, and a difference between a coefficient of expansion of the front substrate from room temperature to 300° C. and a coefficient of expansion of the dielectric layer from room temperature to 300° C. is expressed by a lateral axis, the difference between the coefficients of expansion and the area percentage stay within a region formed by connecting coordinates (35×10?7/° C., 60%), coordinates (8×10?7/° C., 60%), coordinates (5×10?7/° C., 40%), and coordinates (23×10?7/° C., 40%) in the mentioned order with a straight line where the straight line is included.
    Type: Application
    Filed: March 11, 2010
    Publication date: March 17, 2011
    Inventors: Kazuhiro Morioka, Morio Fujitani, Hirofumi Higashi, Shinsuke Yoshida, Akira Kawase, Tatsuo Mifune
  • Patent number: 7764017
    Abstract: A plasma display panel comprises front plate (20) having display electrode (24) formed on a glass substrate with discharge gap (50), and back plate (30) having barrier ribs (34) formed to divide discharge cells, and arranged in a manner to confront the front plate (20). The barrier ribs (34) comprise vertical barrier rib (34a) arranged in parallel to an address electrode and horizontal barrier rib (34b) arranged in a manner to cross the vertical barrier rib (34a), and the vertical barrier rib (34a) has a shape satisfying the formula of H1>H2>H3, where H1 denotes a height of it at crossing portion (56) with the horizontal barrier rib (34b), H2 a height at a position of the discharge gap (50) of the display electrode (24), and H3 a height at a predetermined point between the position of the discharge gap (50) and the position of the crossing portion (56) with the horizontal barrier rib (34b).
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: July 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Morio Fujitani, Keisuke Sumida, Shinichiro Ishino, Kenichi Kusaka
  • Publication number: 20100176721
    Abstract: A plasma display panel including rear glass substrate having address electrode, insulating layer, barrier rib and a phosphor layer thereon. Insulating layer does not contain lead. An average value of a void ratio of a region at a depth of up to 50% from rear glass substrate in a thickness of insulating layer ranges from 5% to 15%. A plasma display panel having a long lifetime and high productivity is achieved.
    Type: Application
    Filed: April 1, 2009
    Publication date: July 15, 2010
    Inventors: Ken Hasegawa, Keisuke Sumida, Morio Fujitani, Kenichi Kusaka, Hideyuki Shirahase, Kohshiroh Mizuno, Koji Aoto, Keiji Horikawa
  • Patent number: 7557504
    Abstract: A plasma display panel can reduce a discharge delay in address discharge, thereby performing high-speed addressing in a stable manner. A front substrate (1) and a back substrate (2) are disposed to face each other, and a discharge space (3) is formed and partitioned by barrier ribs (10) so as to form priming discharge cells (17) and main discharge cells (11). A clearance (19) is provided between the barrier ribs (10) of the priming discharge cells (17) and the front substrate (1), and priming particles generated in the priming discharge cells (17) are supplied to the main discharge cells (11) through the clearance (19), whereby a PDP performing high-speed addressing is obtained.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: July 7, 2009
    Assignee: Panasonic Corporation
    Inventors: Hiroyuki Tachibana, Morio Fujitani, Tsuyoshi Nishio, Toru Ando, Koichi Mizuno
  • Publication number: 20090102378
    Abstract: A plasma display panel comprises front plate (20) having display electrode (24) formed on a glass substrate with discharge gap (50), and back plate (30) having barrier ribs (34) formed to divide discharge cells, and arranged in a manner to confront the front plate (20). The barrier ribs (34) comprise vertical barrier rib (34a) arranged in parallel to an address electrode and horizontal barrier rib (34b) arranged in a manner to cross the vertical barrier rib (34a), and the vertical barrier rib (34a) has a shape satisfying the formula of H1>H2>H3, where H1 denotes a height of it at crossing portion (56) with the horizontal barrier rib (34b), H2 a height at a position of the discharge gap (50) of the display electrode (24), and H3 a height at a predetermined point between the position of the discharge gap (50) and the position of the crossing portion (56) with the horizontal barrier rib (34b).
    Type: Application
    Filed: August 7, 2007
    Publication date: April 23, 2009
    Inventors: Morio Fujitani, Keisuke Sumida, Shinichiro Ishino, Kenichi Kusaka
  • Patent number: 7489079
    Abstract: A plasma display device is provided having improved efficiency and increased image quality. This device includes a pair of front and back substrates opposed to each other to form between the substrates a discharge space partitioned by barrier ribs, a plurality of display electrodes, each of which is formed of a scan electrode and a sustain electrode and disposed on the substrate of a front panel to form a discharge cell between the barrier ribs, a dielectric layer formed above the front substrate to cover the display electrodes, and a phosphor layer which emits light by discharge between the display electrodes. The dielectric layer is constructed of at least two layers of different softening points and is formed with, at its surface closer to the discharge space, a recessed part in each discharge cell. This suppresses extension of the discharge and allows stable formation of the recessed part.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: February 10, 2009
    Assignee: Panasonic Corporation
    Inventor: Morio Fujitani
  • Patent number: 7471042
    Abstract: An object of the present invention is to provide a technique for relatively easily suppressing the yellowing of a Plasma Display Panel in which electrodes comprising silver are disposed on the substrates, and thus render image displays with high luminance and high quality. In order to achieve the object, an arrangement is made in which the electrodes comprising silver further include an element whose standard electrode potential is lower than that of silver, such as Cr, Al, In, B, and Ti, or a compound of such an element, as a silver ionization inhibiting substance.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: December 30, 2008
    Assignee: Panasonic Corporation
    Inventors: Morio Fujitani, Hiroyuki Yonehara, Masaki Aoki, Keisuke Sumida, Hideki Asida, Junichi Hibino, Daisuke Adachi
  • Patent number: 7453206
    Abstract: A PDP has first and second substrates which face each other with a space in between. A display electrode pair and a dielectric layer are formed on the first substrate, and a plurality of discharge cells are formed between the first and second substrates along the display electrode pair. In this construction, two or more depressions are provided in the dielectric layer in an area corresponding to each discharge cell. This improves luminous intensity and illumination efficiency. Also, to form the dielectric layer on the first substrate, first a transfer film is made by providing a dielectric precursor layer on a support film, then depressions are formed in the dielectric precursor layer of the transfer film, and lastly the dielectric precursor layer of the transfer film is transferred onto the first substrate. This decreases the number of manufacturing steps and increases the yield, thereby reducing manufacturing costs.
    Type: Grant
    Filed: May 27, 2002
    Date of Patent: November 18, 2008
    Assignee: Panasonic Corporation
    Inventors: Morio Fujitani, Hiroyuki Yonehara, Masaki Aoki, Keisuke Sumida, Hideki Asida, Junichi Hibino
  • Patent number: 7422503
    Abstract: Disclosed here is a plasma display panel having stable addressing characteristics and a method of manufacturing a plasma display panel having such a reliable structure. According to the plasma display panel and the manufacturing method, on back plate (2) that confronts front plate (1) having scan electrodes (6) and sustain electrodes (7) thereon, data electrodes (10), first dielectric layer (17) disposed to cover the data electrodes, priming electrodes (15), and second dielectric layer (18) disposed to cover the priming electrodes are formed in the order named; at the same time, the softening temperatures of the materials forming the components disposed on the back plate are determined so as to become lower in the order named. The temperature setting protects first dielectric layer (17) from deterioration or deformation, improving dielectric voltage between data electrodes (10) and priming electrodes (15).
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Morio Fujitani, Keisuke Sumida, Tatsuo Mifune, Shinichiro Ishino, Hiroyuki Tachibana
  • Patent number: 7420327
    Abstract: A plasma display panel includes a front panel and a rear panel disposed opposing each other. The front panel includes a display electrode composed of a scan electrode and a sustain electrode extending in a row direction. A rear panel includes address electrode extending in a column direction and intersecting the display electrode. A lattice form of barrier ribs of row direction barrier ribs and column direction barrier ribs, which have the same height, forming a plurality of individually divided discharge cells is provided in a part in which the display electrode and the address electrode intersect each other. The row direction barrier ribs of the barrier ribs are provided with communication portions communicating discharge cells in non-parallel to the column direction.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: September 2, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Morio Fujitani
  • Patent number: 7378796
    Abstract: A plasma display panel has a stable addressing characteristic, no dielectric breakdown, and high reliability. Data electrodes (10), first dielectric layer (17) for covering the data electrodes (10), priming electrodes (15), and second dielectric layer (18) for covering the priming electrodes (15) are sequentially formed on back substrate (2). Slotted parts (10a) are formed in a part of each data electrode (10). Thus, data electrodes (10) are prevented from deforming during the manufacturing, and dielectric voltage between data electrodes (10) and priming electrodes (15) is improved.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Morio Fujitani, Keisuke Sumida, Tatsuo Mifune, Shinichiro Ishino, Hiroyuki Tachibana
  • Patent number: 7319291
    Abstract: A plasma display panel does not cause disadvantages such as exfoliating or chipping in dielectric layers. The plasma display panel includes a first dielectric layer (7) for covering a display electrode which is formed on a front substrate (3) and which consists of a scan electrode and a sustain electrode, and a second dielectric layer for covering a data electrode formed on a back substrate, and the peripheries of the first dielectric layer (7) and/or the second dielectric layer have a radius of curvature of other than 0.
    Type: Grant
    Filed: January 19, 2004
    Date of Patent: January 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Morio Fujitani
  • Patent number: 7151343
    Abstract: A plasma display panel has address properties stabilized. A priming discharge is performed between auxiliary electrodes (18), which are formed on a front substrate (1) and coupled with scan electrodes (6), and priming electrodes (14) formed on a back substrate (2). And on the front substrate (1), a dielectric layer (4) is made thinner in regions corresponding to priming cells (gap parts 13) than in regions corresponding to cell parts (11). As a result, the priming discharge has a wider margin, and a supply of priming particles to the discharge cells is stabilized, whereby a discharge delay during the addressing is reduced, and the address properties are stabilized.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: December 19, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tachibana, Morio Fujitani, Yasuyuki Noguchi, Tetsuya Shirai
  • Publication number: 20060279214
    Abstract: Disclosed here is a plasma display panel having stable addressing characteristics and a method of manufacturing a plasma display panel having such a reliable structure. According to the plasma display panel and the manufacturing method, on back plate (2) that confronts front plate (1) having scan electrodes (6) and sustain electrodes (7) thereon, data electrodes (10), first dielectric layer (17) disposed to cover the data electrodes, priming electrodes (15), and second dielectric layer (18) disposed to cover the priming electrodes are formed in the order named; at the same time, the softening temperatures of the materials forming the components disposed on the back plate are determined so as to become lower in the order named. The temperature setting protects first dielectric layer (17) from deterioration or deformation, improving dielectric voltage between data electrodes (10) and priming electrodes (15).
    Type: Application
    Filed: May 18, 2004
    Publication date: December 14, 2006
    Inventors: Morio Fujitani, Keisuke Sumida, Tatsuo Mifune, Shinichiro Ishino, Hiroyuki Tachibana
  • Publication number: 20060238122
    Abstract: To reduce hydrocarbons existing inside the inner space of a PDP to thereby realize a PDP providing a high-quality picture and having a long life. A catalyst reacting with hydrocarbons is provided on protective layer (8) formed on front panel (1) and barrier ribs (12), phosphor layers (13), and base dielectric layer (11) formed on back panel (2), in an exposed manner to the inner space of the PDP, so that the hydrocarbons are oxidized or decomposed by the catalytic activity of the catalyst with the hydrocarbons.
    Type: Application
    Filed: February 8, 2005
    Publication date: October 26, 2006
    Inventor: Morio Fujitani