Patents by Inventor Morishi Izumita

Morishi Izumita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8196011
    Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: June 5, 2012
    Assignee: Hitachi ULSI Systems Co., Ltd.
    Inventors: Morishi Izumita, Hiroshi Takayanagi
  • Patent number: 7530003
    Abstract: Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: May 5, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Yuan Xing Lee, Morishi Izumita
  • Publication number: 20080320368
    Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.
    Type: Application
    Filed: February 15, 2006
    Publication date: December 25, 2008
    Inventors: Morishi Izumita, Hiroshi Takayanagi
  • Patent number: 7296215
    Abstract: In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: November 13, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Morishi Izumita, Terumi Takashi, Hideki Sawaguchi, Seiichi Mita
  • Patent number: 7268707
    Abstract: Embodiments of the invention allow relatively simple circuits to provide a coding device capable of coding longer bit-length data suitably for disk apparatus and a decoding device capable of decoding the data coded by the coding device. In one embodiment, a coding device comprises: a coder which, based on an M bits code string, produces an (M+1) bits coded string where each of the plural bits which may appear in the M bits code string is limited in run length; a preprocessor which produces an M bits code string by removing (N?M) bits respectively from predefined (N?M) positions of an incoming N bits code string and outputs the M bits code string to the coder; and a postprocessor which produces and outputs an (N+1) bits code string by inserting the (N?M) bits, which are removed by the preprocessor, into predefined (N?M) respective insertion positions of the (M+1) bits coded string output from the coder.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: September 11, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Terumi Takashi, Yoshiju Watanabe, Morishi Izumita, Yasuyuki Itou
  • Patent number: 7245236
    Abstract: Embodiments of the invention a signal processing method capable of realizing low decoding error ratio by using a simple configuration free from unnecessary redundant bits. In one embodiment, user data (512 bytes+additional data) input to an input terminal is RLL-encoded by a RLL encoder 1. The data from the RLL encoder—1 is entered into a symbol error correction encoder where 9-bit symbol encoding is done. Its RS code portion is RLL-encoded by a RLL encoder—2. Signal read from a magnetic disk is entered into a RLL decoder—2 where the RS code portion is RLL-decoded. The signal from the RLL decoder—2 is then entered into a symbol error correction decoder where random read/write errors, burst errors attributable to defects and other errors are corrected to produce a (user data+RLL) signal. This data is output to an output terminal after being decoded by a RLL decoder—1.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: July 17, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Morishi Izumita, Terumi Takashi, Yasuyuki Itou, Masaharu Kondou
  • Publication number: 20060220931
    Abstract: Embodiments of the invention allow relatively simple circuits to provide a coding device capable of coding longer bit-length data suitably for disk apparatus and a decoding device capable of decoding the data coded by the coding device. In one embodiment, a coding device comprises: a coder which, based on an M bits code string, produces an (M+1) bits coded string where each of the plural bits which may appear in the M bits code string is limited in run length; a preprocessor which produces an M bits code string by removing (N-M) bits respectively from predefined (N-M) positions of an incoming N bits code string and outputs the M bits code string to the coder; and a postprocessor which produces and outputs an (N+1) bits code string by inserting the (N-M) bits, which are removed by the preprocessor, into predefined (N-M) respective insertion positions of the (M+1) bits coded string output from the coder.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Terumi Takashi, Yoshiju Watanabe, Morishi Izumita, Yasuyuki Itou
  • Publication number: 20060195760
    Abstract: Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint.
    Type: Application
    Filed: February 17, 2005
    Publication date: August 31, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Yuan Lee, Morishi Izumita
  • Publication number: 20060114137
    Abstract: Embodiments of the invention a signal processing method capable of realizing low decoding error ratio by using a simple configuration free from unnecessary redundant bits. In one embodiment, user data (512 bytes+additional data) input to an input terminal is RLL-encoded by a RLL encoder 1. The data from the RLL encoder—1 is entered into a symbol error correction encoder where 9-bit symbol encoding is done. Its RS code portion is RLL-encoded by a RLL encoder—2. Signal read from a magnetic disk is entered into a RLL decoder—2 where the RS code portion is RLL-decoded. The signal from the RLL decoder—2 is then entered into a symbol error correction decoder where random read/write errors, burst errors attributable to defects and other errors are corrected to produce a (user data+RLL) signal. This data is output to an output terminal after being decoded by a RLL decoder—1.
    Type: Application
    Filed: November 15, 2005
    Publication date: June 1, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Morishi Izumita, Terumi Takashi, Yasuyuki Itou, Masaharu Kondou
  • Publication number: 20050044468
    Abstract: In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 24, 2005
    Applicants: Hitachi Global Storage Technologies, Japan, Ltd., Toyota Technological Institute
    Inventors: Morishi Izumita, Terumi Takashi, Hideki Sawaguchi, Seiichi Mita
  • Patent number: 6731441
    Abstract: Here is disclosed an information recording and reproducing apparatus comprising a multi-phase quadrature angular modulator for subjecting a signal to be written on a recording medium to multi-phase quadrature angular modulation to generate a modulated signal expressing information in phase difference and frequency difference, a quantizer for generating a discrete signal by making discrete the amplitude of the modulated signal generated by the quadrature angular modulator with reference to a certain level, a write head for writing the output signal of the quantizer onto the recording medium, a read head for reading information written on the recording medium, a read compensate circuit for compensating the phase and amplitude of a signal readout of the read head, and a multi-phase quadrature angular demodulator for demodulating a signal supplied from the read compensate circuit by subjecting it to multi-phase quadrature angular demodulation.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: May 4, 2004
    Assignees: Hitachi, Ltd., Toyota School Foundation
    Inventors: Hideaki Maeda, Morishi Izumita, Terumi Takashi, Seiichi Mita
  • Publication number: 20030067696
    Abstract: Here is disclosed an information recording and reproducing apparatus comprising a multi-phase quadrature angular modulator for subjecting a signal to be written on a recording medium to multi-phase quadrature angular modulation to generate a modulated signal expressing information in phase difference and frequency difference, a quantizer for generating a discrete signal by making discrete the amplitude of the modulated signal generated by the quadrature angular modulator with reference to a certain level, a write head for writing the output signal of the quantizer onto the recording medium, a read head for reading information written on the recording medium, a read compensate circuit for compensating the phase and amplitude of a signal readout of the read head, and a multi-phase quadrature angular demodulator for demodulating a signal supplied from the read compensate circuit by subjecting it to multi-phase quadrature angular demodulation.
    Type: Application
    Filed: August 9, 2002
    Publication date: April 10, 2003
    Inventors: Hideaki Maeda, Morishi Izumita, Terumi Takashi, Seiichi Mita
  • Patent number: 5151924
    Abstract: An automatic equalization apparatus useful for supplying an output signal of a transversal filter simultaneously to two juxtaposed comparators, one of the two comparators performing signal identification, the other of the two comparators detecting an equalization error with the reference level changed, and extracting data from resultant two kinds of data trains by taking at least (N-1)/2+1 bits as the unit, N being the number of taps of the transversal filter, performing correlation computation, and setting tap coefficients of the transversal filter on the basis of the resultant accumulated value.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: September 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Seiichi Mita, Morishi Izumita, Hiroshi Ide, Nobukazu Doi, Yoshinori Okada, Yasuo Inagaki
  • Patent number: 5131011
    Abstract: Non-linear intersymbol interference and noise in a received data signal are corrected through use of a Viterbi detector which estimates the most likely sequence of transmitted data symbols by keeping track of candidate data sequence that are recursively updated, based on likelihood measures which are determined by a signal processor which includes circuits for estimating hypothesized channel outputs in the absence of noise. Non-linear input-output relations are stored in one or more look-up tables which, in a preferred embodiment, are registers that store hypothesized channel output symbols in the absence of noise. The contents of the look-up tables may be modified in response to an error signal representative of the difference of the channel output signal and the look-up table output signal.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: July 14, 1992
    Assignees: N. V. Philips' Gloeilampenfabrieken, Hitachi, Ltd.
    Inventors: Johannes W. M. Bergmans, Seiichi Mita, Morishi Izumita
  • Patent number: 5090005
    Abstract: A tape recorder of the present invention comprises a pair of feed and take-up spools for winding a tape as recording media, a rotatable drum rotated to wind and run the tape between the pair of spools over the drum surface helically, a head for recording, reproducing or erasing signals on the tape wound over said drum surface, and control means for controlling the relative positional relationship between the head and the tape wound over the drum surface based on an error signal such that said signals are stably recorded, reproduced or erased along a desired track, the control means having means for holding the error signal during the period in which the tape is discontinued over a drum surface.
    Type: Grant
    Filed: October 30, 1989
    Date of Patent: February 18, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Hara, Seiichi Mita, Morishi Izumita, Hiroyuki Tsuchinaga
  • Patent number: 5047852
    Abstract: An adaptive transform encoder can keep a recording rate of a digital signal at a constant level.
    Type: Grant
    Filed: July 5, 1989
    Date of Patent: September 10, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Hanyu, Nobukazu Doi, Seiichi Mita, Morishi Izumita, Yoshizumi Eto
  • Patent number: 5036524
    Abstract: In a system for transmitting a binary source signal from a data transmitter to a data receiver through a noisy dispersive channel, the data transmitter includes a sliding block encoder which converts the binary source signal at a given symbol rate 1/T into an encoded binary data signal at a symbol rate P/(NT), where P and N are positive integers such that N/P.ltoreq..sup.2 log(3)/2= 0.79248. Since the channel introduces intersymbol interference and noise into the encoded data signal, the data receiver is formed from the cascade of an equalizer, a sampler and a reconstruction circuit which serves to reconstruct the binary source signal at the symbol rate 1/T. The reconstruction circuit includes a detector in a cascade with a decoder having memory the equalizer, sampler and detector are arranged for the detection of a ternary data signal at the symbol rate P/(2NT).
    Type: Grant
    Filed: January 29, 1990
    Date of Patent: July 30, 1991
    Assignees: N.V. Philips' Gloeilampenfabrieken, Hitachi Ltd.
    Inventors: Johannes W. M. Bergmans, Seiichi Mita, Morishi Izumita, Nobukazu Doi
  • Patent number: 5005184
    Abstract: A waveform equalization method whereby a transversal filter having 5 or more tapes is included, and a difference signal output, which is obtained when an isolated impulse response waveform of a digital modulated signal is inputted to the above described filter and the output of the filter is inputted to an adder, is allowed to have intersymbol interference at .+-.T/2 with respect to the central axis time and has zero outputs at .+-.nT/2 (where n.gtoreq.2 and n is an integer).
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: April 2, 1991
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha, Hitachi Video Engineering, Inc.
    Inventors: Tetsuya Amano, Seiichi Mita, Morishi Izumita, Nobukazu Doi, Mamoru Kaneko, Hiroto Yamauchi, Susumu Kasai
  • Patent number: 4983965
    Abstract: An original digital signal is converted into either a Miller-squared code signal or a Miller code signal, and undergoes serial-to-parallel conversion to produce n-phase signals (where n is desired to be a positive even number). N-phase virtual demodulated signals are simultaneously generated at clock timing having a period equivalent to 1/n times the period of the transmission clock. Out of the n-phase virtual demodulated signals, n/2 phases are selected to undergo parallel-to-serial conversion, the original digital signal being thus obtained.
    Type: Grant
    Filed: December 4, 1989
    Date of Patent: January 8, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Nobukazu Doi, Morishi Izumita, Seiichi Mita, Yoshizumi Eto
  • Patent number: 4970707
    Abstract: An optical tape apparatus having improved focus and tracking control. An optical head records, reproduces, or rewrites data on an optical tape by helically scanning the tape with a laser beam. A guide plate is disposed between the optical head and the tape to prevent the beam from becoming unfocused due to fluctuation of the tape cuased by an air film between the optical head and the tape. The optical head contains a semiconductor laser and an optical system exhibiting chromatic aberration for directing the laser beam onto the tape. The optical system includes a condenser lens for focusing the beam onto the tape. Fine focus control is achieved by changing the wavelength of the laser beam by directing part of the beam reflected from the tape back to the laser, thereby changing the focal point of the beam by virtue of the chromatic aberration of the optical system.
    Type: Grant
    Filed: September 1, 1988
    Date of Patent: November 13, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Hara, Yoshito Tsunoda, Shigeru Nakamura, Yoshizumi Eto, Seiichi Mita, Morishi Izumita, Hiroyuki Tsuchinaga, Masuo Kasai