Abstract: In addition to transmitting over the ASIC-NAND bus the legacy long command format, a data storage device will be able to use also a compressed/improved command format. The alternate command's format is hidden from most parts of the NAND. The NAND can have a layer that will translate compressed/non standard commands to the legacy (standard) format for use by the rest of the NAND device's logic, as currently implemented. According to selected command format, the Low Level Flow Sequencer (LLFS) sequence generator and the flash interface module (FIM) will know which format to use in order to encode the command's content for transmission to the NAND by the FIM/ASIC/controller. The command is then executed on the NAND side according to the selected command scheme. Changes will be applied in the device controller on the ASIC side—to encode the command, and on the NAND side—to decode the command according to the selected format.

Abstract: According to the selected command format mode, the same opcode of existing commands will now be able to be sent using a new command format that will compress the large command and achieve the same functionality as the original large command. Examples of such include address compression, repeated fields, unnecessary known fields, etc. Instead of a long address being sent across the ASIC-NAND bus, the address sent over the bus will be represented using less bits with lower granularity. The controller will not send known repeated elements e.g. of the long address in the new format utilizing the compressed command such that the address can be transmitted only once instead of several times per each command. The new format will not include parts of the commands that are defined by the standard when it is possible to eliminate their transmission. The new command format will have two or more supported versions some of the commands, allowing introduction of new flexibility and improved performance of the device.

Abstract: A data storage device for providing failure recovery may include a device memory including one or more memories and a command history buffer. The device memory may be configured to receive and process (i) commands directed to the one or more memories, and (ii) an access command for accessing the command history buffer. The command history buffer may be configured to store information related to the commands. The data storage device may also include a controller coupled to the device memory and configured to: send the commands to the device memory; retrieve information stored in the command history buffer from the device memory, by issuing the access command; and in accordance with a determination that the information stored in the command history buffer indicates invalid command flows, resend at least a portion of the commands to the device memory.