Abstract: According to one embodiment, a port connection circuit includes a controller includes a first port configured to selectively switch to an input state or to an output state, a second port configured to output a switch control signal, a third port configured to detect an event, an input contact connected to or disconnected from an output contact of an external connector and connected to the third port, a switch connected between the input contact and the first port, and a switch control circuit configured to close or open the switch based on a voltage of the input contact.

Abstract: According to one embodiment, a port connection circuit includes a controller includes a first port configured to selectively switch to an input state or to an output state, a second port configured to output a switch control signal, a third port configured to detect an event, an input contact connected to or disconnected from an output contact of an external connector and connected to the third port, a switch connected between the input contact and the first port, and a switch control circuit configured to close or open the switch based on a voltage of the input contact.

Abstract: In one embodiment, a port connection circuit includes a controller, an input contact, a switch, and a switch control circuit. The controller comprises a first port to selectively switch to an input or output state, a second port configured to output a switch control signal, and a third port configured to detect an event. The input contact is connected to an output contact of an external connector and the third port. The switch is connected between the input contact and the first port. The switch control circuit is configured to close or open the switch based on a voltage of the input contact. The switch control circuit includes a hysteresis circuit to which this voltage is input, and an OR gate that logically adds an output of the hysteresis circuit and a switch control signal from the second port and outputs the result to a control contact of the switch.

Abstract: According to one embodiment, a port connection circuit includes a controller includes a first port configured to selectively switch to an input state or to an output state, a second port configured to output a switch control signal, a third port configured to detect an event, an input contact connected to or disconnected from an output contact of an external connector and connected to the third port, a switch connected between the input contact and the first port, and a switch control circuit configured to close or open the switch based on a voltage of the input contact.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: There is provided an electronic apparatus including a first interface to which a first device is connectable, a second interface to which a second device is connectable, and a power supply control circuit that controls a current to be supplied to the first and second interfaces. With the above arrangement, the power supply can efficiently be controlled for a plurality of interfaces without increasing the number of power supply control circuits.

Abstract: According to one embodiment, an electronic apparatus including an driving unit configured to drive an expansion unit which is detachably loaded, and a communication controller configured to control communication with the driving unit via an interface which can be electrically disconnected with power turned on, the driving unit includes a detection unit configured to detect loading/unloading of the expansion unit, and an interface control unit configured to control the interface so as to disable the interface if unloading of the expansion unit is detected by the detection unit and to allow the communication controller to determine enabling/disabling of the interface if loading of the expansion unit is detected.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: In a computer system, it is determined whether current operational frequencies of a memory and a CPU, which have been detected, coincide with operable frequencies of a memory system. When it has been determined that the current operational frequencies of the memory and the CPU coincide with the operable frequencies of the memory system, it is determined whether the current operational frequencies of the memory and the CPU coincide with individual operable frequencies of the memory and the CPU. When non-coincidence has been determined, the current operational frequencies of the memory and the CPU, which have been determined to be non-coincident, are set at the operable frequencies of the memory system corresponding to the current operational frequencies of the memory and the CPU which have been determined to be non-coincident.

Abstract: An information processing apparatus includes a device controller which executes communication with an I/O device via a communication channel, the controller including a first internal circuit and a first input/output buffer connected to the communication channel, and the I/O device including a second internal circuit and a second input/output buffer connected to the communication channel, a power supply unit which is capable of supplying combinations of an operation voltage for driving the first and second internal circuits and an interface voltage for driving the first and second input/output buffers to the I/O device and the controller, a unit which executes an operation test with including data transfer between the I/O device and the controller with respect to a predetermined combinations of the operation voltage and the interface voltage, and a unit which selects one of the combinations based on a result of the operation test.

Abstract: When the system of an information processing apparatus is set to effectively perform a wake-up function in response to a specified event including reception of a signal from a radio communication system, such as Bluetooth, there is a possibility of the resume process being performed under an unsteady condition where the apparatus is liable to receive vibration or shock. In this case, a vibration-resistant memory device, such as a semiconductor memory device, is forcibly selected as the place for storing the operating status by the suspend/resume function regardless of the user's selection, even if a hard disk drive which is less vibration-resistant is selected as the storage place.

Abstract: There is provided an electronic apparatus including a first interface to which a first device is connectable, a second interface to which a second device is connectable, and a power supply control circuit that controls a current to be supplied to the first and second interfaces. With the above arrangement, the power supply can efficiently be controlled for a plurality of interfaces without increasing the number of power supply control circuits.

Abstract: In a computer system, it is determined whether current operational frequencies of a memory and a CPU, which have been detected, coincide with operable frequencies of a memory system. When it has been determined that the current operational frequencies of the memory and the CPU coincide with the operable frequencies of the memory system, it is determined whether the current operational frequencies of the memory and the CPU coincide with individual operable frequencies of the memory and the CPU. When non-coincidence has been determined, the current operational frequencies of the memory and the CPU, which have been determined to be non-coincident, are set at the operable frequencies of the memory system corresponding to the current operational frequencies of the memory and the CPU which have been determined to be non-coincident.

Abstract: When a CPU enters the sleep mode, an L2 cache with the ZZ terminal is also switched to the sleep mode simultaneously. When the CPU returns from the sleep mode, the L2 cache is simultaneously switched from the sleep mode to the normal operation mode. Since the normal operation of the cache is not ensured for a fixed period of time from when it leaves the sleep mode, the cache is placed in the disabled state in which its use is prohibited before being switched to the sleep mode and returned to the enabled state in which its use is allowed after a lapse of a fixed period of time from when it leaves the sleep mode.

Abstract: An interface for a high-performance graphics adapter is provided. In a computer system which includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer program running on the host processor utilizes a graphics operating system, such as an Extended Graphics Array Input/Output System (XGA BIOS) to write graphics data in XGA format to the memory. A controller translates memory addresses generated by the XGA BIOS (and hence the host processor) into memory addresses recognized by the coprocessor. One or more graphics controllers selectively swap pixel data between Intel order and Motorola order and store the graphics data, into an XGA video-random-access memory (RAM) buffer. A back-end gate array parallel-serial converts input display data in units of designated pixel data, and the graphics data is displayed on a CRT.

Abstract: An interface for a high-performance graphics adapter is provided. A computer system includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer program running on the host processor utilizes a graphics operating system, such as an Extended Graphics Array Input/Output System (XGA BIOS) to write graphics data in XGA format to the memory. A totally awesome controller translates memory addresses generated by the XGA BIOS (and hence the host processor) into memory addresses recognized by the coprocessor. One or more graphics controllers selectively swap pixel data between Intel order and Motorola order and store the graphics data, into an XGA video-random-access memory (RAM) buffer. A back-end gate array parallel-serial converts input display data in units of designated pixel data, and the graphics data is displayed on a CRT.

Abstract: An interface for a high-performance graphics adapter is provided. In a computer system which includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer program running on the host processor utilizes a graphics operating system, such as an Extended Graphics Array Input/Output System (XGA BIOS) to write graphics data in XGA format to the memory. A totally awesome controller translates memory addresses generated by the XGA BIOS (and hence the host processor) into memory addresses recognized by the coprocessor. One or more graphics controllers selectively swap pixel data between Intel order and Motorola order and store the graphics data, into an XGA video-random-access memory (RAM) buffer. A back-end gate array parallel-serial converts input display data in units of designated pixel data, and the graphics data is displayed on a CRT.