Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.

Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.

Abstract: A storage device includes a nonvolatile semiconductor memory and a controller. The controller is configured to predict power consumption that is required to carry out operations in accordance with access pattern and throughput received from a host, notify the predicted power consumption to the host, determine operating resources of at least one of the nonvolatile semiconductor memory and the controller to carry out the operations, on the basis of the permissible power consumption received from the host, and carry out the operations using the determined operating resources.

Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.

Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.

Abstract: A storage device includes a nonvolatile semiconductor memory and a controller.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a buffer memory, a power management unit, and a controller. The buffer memory is divided into a plurality of first subbuffers. The power management unit acquires a power consumption value. The power management unit starts and stops power supply to the first subbuffers with respect to each first subbuffer, based on the acquired power consumption value. The controller selects a second subbuffer from one or more third subbuffers being supplied with power. The controller buffers transfer data between the outside and the nonvolatile memory in the second subbuffer.

Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.

Abstract: According to one embodiment, a memory controller includes a front end section and a back end section. The front end section receives commands from a host and returns responses to the commands to the host. The back end section receives the commands from the front end section and has access to a non-volatile memory unit in response to the commands. The front end section controls, on the basis of target performance, a number of the commands which are to be transmitted to the back end section from a queue. The back end section controls the number of commands which are to be input on the basis of a target power consumption value.

Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller is configured to control data input to, and output from, nonvolatile memories for channels. The encoding module is configured to generate encoded data for which an inter-channel error correction process, using data stored in each of the nonvolatile memories. The data controller is configured to manage the encoded data in units of logic blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to one plane in each logic block.

Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.

Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

Abstract: According to one embodiment, a data storage apparatus includes a memory module and a controller. The memory module has a plurality of flash memory chips. Data is written to or read from each flash memory chip having a specific page size as access unit. The controller is configured to supply memory control signals, which are independent of the common signal containing the data and addresses, to the flash memory chips, respectively, in order to write data larger than the specific data size to the memory module. In the memory module, the respective flash memory chips store the data, each at the same address, in response to the memory control signals.

Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.

Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller is configured to control data input to, and output from, nonvolatile memories for channels. The encoding module is configured to generate encoded data for which an inter-channel error correction process, using data stored in each of the nonvolatile memories. The data controller is configured to manage the encoded data in units of logic blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to one plane in each logic block.

Abstract: According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory.

Abstract: According to one embodiment, a memory control device includes a first controller, a second controller, an access module, and a response sort module. The first controller controls processing of a data access command to a nonvolatile memory from a host. The second controller controls processing assigned to the second controller between the first controller and the second controller. The access module performs data access to the nonvolatile memory in response to a command from the first controller or the second controller. When an error occurs in the data access by the access module, the response sort module returns a response to the second controller instead of the first controller.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

Abstract: According to one embodiment, there is provided a bifocal display device includes a database that manages at least distant and nearby viewpoint images as data files, an image processing circuit that obtains a far viewpoint image and a nearby viewpoint image from the data base, blurs contours of the far viewpoint image, emphasizes contours of the nearby viewpoint image, and performs an image processing of superimposing the blurred far viewpoint image and the emphasized nearby viewpoint image on each other, and a display that displays a result of the image processing.