Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Abstract: A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control section for writing data which is held by the first storage section and whose amount corresponds to the unit area, into the non-volatile memory in a unit area-by-unit area basis, and writing data which is held by the first storage section and whose amount is less than the unit area, into a second storage section, and a second control section for writing data held by the second storage section into the non-volatile memory.

Abstract: While a plurality of physical address memories are provided with respect to one logical address of a non-volatile memory device, an empty physical address memory contained in the plural physical address memories is searched with respect to a writing operation for one logical address, and then, data is written in this empty physical address memory. With respect to a reading operation for one logical address, such a physical address memory to which data has been written at last is searched, and the storage content of this memory is read out. As a result, the data rewriting operation to a non-volatile memory can be carried out with employment of the simple circuit arrangement with respect to one logical address, while an erasing operation is not performed, and an area of a memory device is not increased but also a total number of data rewriting operation is not limited to a number defined in a specification of the memory device.

Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Abstract: A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110.

Abstract: While a plurality of physical address memories are provided with respect to one logical address of a non-volatile memory device, an empty physical address memory contained in the plural physical address memories is searched with respect to a writing operation for one logical address, and then, data is written in this empty physical address memory. With respect to a reading operation for one logical address, such a physical address memory to which data has been written at last is searched, and the storage content of this memory is read out. As a result, the data rewriting operation to a non-volatile memory can be carried out with employment of the simple circuit arrangement with respect to one logical address, while an erasing operation is not performed, and an area of a memory device is not increased but also a total number of data rewriting operation is not limited to a number defined in a specification of the memory device.

Abstract: A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110.