Patents by Inventor Mu-hui Park
Mu-hui Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11948631Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phis change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.Type: GrantFiled: May 7, 2021Date of Patent: April 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae Hui Na, Mu Hui Park, Kwang Jin Lee, Yong Jun Lee
-
Publication number: 20210264975Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phis change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Inventors: Tae Hui NA, Mu Hui PARK, Kwang Jin LEE, Yong Jun LEE
-
Patent number: 11056187Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phase-change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.Type: GrantFiled: July 13, 2018Date of Patent: July 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae Hui Na, Mu Hui Park, Kwang Jin Lee, Yong Jun Lee
-
Patent number: 10784311Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.Type: GrantFiled: July 5, 2019Date of Patent: September 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-Hui Park, Wooyeong Cho
-
Patent number: 10770138Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.Type: GrantFiled: December 19, 2019Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Won Kim, Mu-Hui Park
-
Publication number: 20200126617Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: HEE-WON KIM, MU-HUI PARK
-
Patent number: 10546637Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.Type: GrantFiled: July 17, 2018Date of Patent: January 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Won Kim, Mu-Hui Park
-
Publication number: 20190333967Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Inventors: MU-HUI PARK, WOOYEONG CHO
-
Patent number: 10388699Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.Type: GrantFiled: May 4, 2017Date of Patent: August 20, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-Hui Park, Wooyeong Cho
-
Publication number: 20190214078Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.Type: ApplicationFiled: July 17, 2018Publication date: July 11, 2019Inventors: HEE-WON KIM, MU-HUI PARK
-
Publication number: 20190164601Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phase-change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.Type: ApplicationFiled: July 13, 2018Publication date: May 30, 2019Inventors: Tae Hui NA, Mu Hui PARK, Kwang Jin LEE, Yong Jun LEE
-
Patent number: 10102897Abstract: A memory device includes: a resistive memory cell connected to a first node; a current supply unit providing to a sensing node a comparison current to be compared with a cell current flowing through the first node to read data stored in the resistive memory cell; a clamping unit connected between the sensing node and the first node and including a transistor and a capacitor connected to a gate of the transistor via a second node; and a sense amplifier sensing the sensing node voltage and transitioning an output value when the sensing node voltage is less than a reference voltage. The clamping unit receives a first read voltage and a boost voltage, ramps up a voltage of the first node in a first precharge mode, and adjusts a level of a second read voltage of the second node in a second precharge mode.Type: GrantFiled: September 6, 2017Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventor: Mu Hui Park
-
Patent number: 10083746Abstract: A memory device and a method for operating the memory device are provided. A resistive memory cell connected to a first node and configured to include a variable resistive element and an access element for controlling a current flowing through the variable resistive element. A detection circuit detects a threshold voltage of the access element and provides a detection current to a sensing node. A clamping circuit connected between the first node and the sensing node receives a first read voltage and ramps up a voltage of the first node. The first node is discharged by a discharge circuit when the detection current becomes equal to a bit line current flowing through the first node while the clamping circuit ramps up the voltage of the first node. A sense amplifier transitions an output voltage value when a voltage level of the sensing node becomes lower than a reference voltage.Type: GrantFiled: August 23, 2017Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Mu Hui Park
-
Publication number: 20180247685Abstract: A memory device includes: a resistive memory cell connected to a first node; a current supply unit providing to a sensing node a comparison current to be compared with a cell current flowing through the first node to read data stored in the resistive memory cell; a clamping unit connected between the sensing node and the first node and including a transistor and a capacitor connected to a gate of the transistor via a second node; and a sense amplifier sensing the sensing node voltage and transitioning an output value when the sensing node voltage is less than a reference voltage. The clamping unit receives a first read voltage and a boost voltage, ramps up a voltage of the first node in a first precharge mode, and adjusts a level of a second read voltage of the second node in a second precharge mode.Type: ApplicationFiled: September 6, 2017Publication date: August 30, 2018Inventor: MU HUI PARK
-
Publication number: 20180166136Abstract: A memory device and a method for operating the memory device are provided. A resistive memory cell connected to a first node and configured to include a variable resistive element and an access element for controlling a current flowing through the variable resistive element. A detection circuit detects a threshold voltage of the access element and provides a detection current to a sensing node. A clamping circuit connected between the first node and the sensing node receives a first read voltage and ramps up a voltage of the first node. The first node is discharged by a discharge circuit when the detection current becomes equal to a bit line current flowing through the first node while the clamping circuit ramps up the voltage of the first node. A sense amplifier transitions an output voltage value when a voltage level of the sensing node becomes lower than a reference voltage.Type: ApplicationFiled: August 23, 2017Publication date: June 14, 2018Inventor: Mu Hui Park
-
Publication number: 20180012937Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.Type: ApplicationFiled: May 4, 2017Publication date: January 11, 2018Inventors: MU-HUI PARK, WOOYEONG CHO
-
Patent number: 9805807Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.Type: GrantFiled: January 21, 2016Date of Patent: October 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon An Lee, Mu-Hui Park, Jiho Cho, Ji-Young Lee, Yoon-Hee Choi
-
Patent number: 9728254Abstract: A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.Type: GrantFiled: September 22, 2016Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventor: Mu-Hui Park
-
Patent number: 9627056Abstract: A resistive memory device comprising: a memory cell having a programmable resistance representing stored data; and a read circuit configured to be connected to the memory cell via a first signal line and read the stored data, wherein the read circuit includes: a voltage controller configured to control a first voltage of the first signal line to be a constant voltage and output a signal to a sensing node; and a sense amplifier connected to the voltage controller via the sensing node, and configured to compare a sensing voltage of the sensing node with a reference voltage.Type: GrantFiled: January 28, 2016Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mu-hui Park, Yeong-taek Lee, Dae-seok Byeon
-
Publication number: 20170011796Abstract: A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.Type: ApplicationFiled: September 22, 2016Publication date: January 12, 2017Inventor: MU-HUI PARK