Abstract: An NVM array includes a plurality of NVM cells, a plurality of word lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of source lines. Each of the NVM cells includes a PMOS select transistor and a PMOS floating gate transistor serially connected to the PMOS select transistor. Each word line is electrically connected to the select gate of the PMOS select transistor. Each bit line is electrically connected to a doping region of the PMOS floating gate transistor of each of the plurality of NVM cells. Each source line is electrically connected to a doping region of the PMOS select transistor.

Abstract: An NVM array includes a plurality of NVM cells, a plurality of word lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of source lines. Each of the NVM cells includes a PMOS select transistor and a PMOS floating gate transistor serially connected to the PMOS select transistor. Each word line is electrically connected to the select gate of the PMOS select transistor. Each bit line is electrically connected to a doping region of the PMOS floating gate transistor of each of the plurality of NVM cells. Each source line is electrically connected to a doping region of the PMOS select transistor.

Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.

Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first oxide define (OD) region and a second oxide define (OD) region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.

Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first OD region and a second OD region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.

Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.