Patents by Inventor Mu-Yue Hsiao

Mu-Yue Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6519736
    Abstract: Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6463563
    Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6460157
    Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6457154
    Abstract: Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6179207
    Abstract: A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: January 30, 2001
    Assignee: International Business Machines Corporation
    Inventors: Douglas Craig Bossen, Chin-Long Chen, Fredrick Hayes Dill, Douglas Seymore Goodman, Mu-Yue Hsiao, Paul Vincent McCann, James Michael Mulligan, Ricky Allen Rand
  • Patent number: 5768294
    Abstract: An apparatus and method is discussed using a parity check matrix in order to acheive correction and detection of errors particularly pertaining to detection data fetched from a wrong address. The code structure enhances utilization of chip reliability by encoding and decoding digital signals through the utilization of a parity check matrix and parity bits generated from system address bits of a computer system with k symbols and b bits per symbol.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: June 16, 1998
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Patent number: 5761221
    Abstract: A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Klaus Ruediger Baat, Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Patent number: 5757823
    Abstract: Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a single bit error in another symbol for use in computer memory systems. The code structure enhances utilization of chip real estate and specifically provides for the utilization of a (76,64) code which employs 19 chips per computer memory word as opposed to 20 chips per word.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: May 26, 1998
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao
  • Patent number: 5751745
    Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: May 12, 1998
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Patent number: 5691996
    Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: November 25, 1997
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Patent number: 5581071
    Abstract: A barcode scanner, which is particularly suitable for reading barcode information from surfaces having various reflective properties, includes a light intensity control for the light source of the barcode scanner. The light intensity control preferably comprises a means for ramping voltage and a summing circuit which allows the current flowing through the light source to be controlled. In addition, the light intensity control utilizes a clocking means which controls the rate of voltage ramping.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: December 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Surasak K. O'Trakoun, Charles F. Pells, William W. Shen
  • Patent number: 5552591
    Abstract: A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: September 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. Bossen, Chin-Long Chen, Frederick H. Dill, Douglas S. Goodman, Mu-Yue Hsiao, Paul V. McCann, James M. Mulligan, Ricky A. Rand
  • Patent number: 5537431
    Abstract: A method and apparatus reliably and robustly decode single width bar codes that may be placed on a variety of materials. The decoding is independent of whether or not the bar code represents dark bars on a light background or light bars on a dark background. The decoder may be implemented either in hardware or as part of a program in a stored program general purpose computer. The signal processing approach taken generates gap sequence information from width sequence information to match predetermined gap sequence patterns. The method and apparatus of the present invention are also particularly amenable to independent creation of the gap sequences from three different techniques which are independent and which thus add robustness to the system. Lastly, the decoding method of the present invention takes advantage of a preprocessing function to remove any certain forms of noise that may be present in the scanned data.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: July 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao
  • Patent number: 5521709
    Abstract: A method and apparatus is provided for producing single width barcodes in a continuous, serpentine pattern. This pattern provides continuity of operation for laser marking instruments and thereby results in the formation of more uniform and higher quality barcode indicia. The use of a continuous serpentine pattern also increases the speed at which the code may be written onto a substrate. This marking method is particularly appropriate for use in marking a wide variety of materials including semiconductors, metals, plastics and ceramics.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. Bossen, Chin-Long Chen, Fuad E. Doany, Mu-Yue Hsiao, Ricky A. Rand, Ralf J. Terbruggen
  • Patent number: 5380998
    Abstract: A single width bar code is appended with an end mark which includes a blank interval and a bar. The resulting bar code is bidirectional and inherently self clocking so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described are robust, reliable, and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
    Type: Grant
    Filed: June 3, 1993
    Date of Patent: January 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. Bossen, Chin-Long Chen, Mu-Yue Hsiao, James M. Mulligan
  • Patent number: 5161163
    Abstract: An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes. The system is also extendable to any system employing an odd number of code symbols that may be present in a single character position.
    Type: Grant
    Filed: August 6, 1991
    Date of Patent: November 3, 1992
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. Bossen, Chin-Long Chen, Mu-Yue Hsiao
  • Patent number: 5070504
    Abstract: An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes. The system is also extendable to any system employing an odd number of code symbols that may be present in a single character position.
    Type: Grant
    Filed: June 23, 1989
    Date of Patent: December 3, 1991
    Assignee: International Business Machines
    Inventors: Douglas D. Bossen, Chin-Long Chen, Mu-Yue Hsiao
  • Patent number: 4461001
    Abstract: Swapping of bits between different words of a memory is accomplished by reference to data on bad bits in the memory. This data controls address inputs to each bit in a memory word so that any word with multiple uncorrectable data is changed to a correctable data word by placing one or more of the bad bits in the word into another word of the memory. The swapping is done by an exclusionary process which deselects certain combinations of addresses thereby limiting the selection process to other combinations. The process can involve categorizing of failures in accordance with type and performing algorithm operations which identify combinations of bit addresses that would result in combining the failures so that there are more errors in any memory word than would be correctable by the error correction code monitoring the memory.
    Type: Grant
    Filed: March 29, 1982
    Date of Patent: July 17, 1984
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. Bossen, Mu-Yue Hsiao