Patents by Inventor Muhammed Ayman Shibib

Muhammed Ayman Shibib has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190393693
    Abstract: A protection circuit can include a first clamping sub-circuit, a first switching sub-circuit and a first resistive sub-circuit coupled in series between a first and second node. The protection circuit can also include a second clamping sub-circuit, a second switching sub-circuit and a second resistive sub-circuit coupled in series between the second and first nodes. The first and second clamping sub-circuits and the first and second resistive sub-circuits can be configured to bias a switching shunt sub-circuit. The switching shunt sub-circuit can be configured to short the first and second nodes together in response to a bias potential from the first and second clamping sub-circuits and the first and second resistive sub-circuits indicative of an over-voltage, Electrostatic Discharge (ESO) or similar event. The first and second switching sub-circuits can be configured to prevent the occurrence of a current path through the first and second resistive sub-circuits at the same time.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Muhammed Ayman Shibib, Chungchi Gina Liao
  • Patent number: 8648445
    Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Agere Systems LLC
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 8580644
    Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Publication number: 20120211834
    Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
    Type: Application
    Filed: May 1, 2012
    Publication date: August 23, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Publication number: 20120175702
    Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 12, 2012
    Applicant: LSI Corporation
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 8193565
    Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Patent number: 8153484
    Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: April 10, 2012
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7820517
    Abstract: In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimiz
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: October 26, 2010
    Assignee: Agere Systems Inc.
    Inventors: Peter L. Gammel, Isik C. Kizilyalli, Marco G. Mastrapasqua, Muhammed Ayman Shibib, Zhijian Xie, Shuming Xu
  • Publication number: 20100123171
    Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
    Type: Application
    Filed: April 17, 2009
    Publication date: May 20, 2010
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Patent number: 7579245
    Abstract: An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 25, 2009
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Publication number: 20080296636
    Abstract: According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage.
    Type: Application
    Filed: June 2, 2008
    Publication date: December 4, 2008
    Inventors: Mohamed N. Darwish, Richard A. Harris, Muhammed Ayman Shibib, Andrew J. Morrish, Robert Kuo-Chang Yang
  • Patent number: 7335565
    Abstract: A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and second source/drain regions of the second conductivity type in the second layer proximate the upper surface of the second layer, the first source/drain region being spaced laterally from the second source/drain region, the gate being formed at least partially between the first and second source/drain regions; and forming at least one electrically conductive trench in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: February 26, 2008
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7329922
    Abstract: An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 12, 2008
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7297606
    Abstract: An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: November 20, 2007
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7279744
    Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: October 9, 2007
    Assignee: Agere Systems Inc.
    Inventors: Peter L. Gammel, Isik C. Kizilyalli, Marco G. Mastrapasqua, Muhammed Ayman Shibib, Zhijian Xie, Shuming Xu
  • Patent number: 7190563
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting a circuit from an ESD event, the ESD protection circuit comprises a metal-oxide semiconductor (MOS) device including a gate terminal, a first source/drain terminal, a second source/drain terminal and a bulk terminal, the bulk and first source/drain terminals being operatively coupled across the circuit to be protected, the gate and second source/drain terminals being coupled together; and a voltage generation circuit coupled between the bulk and gate terminals of the MOS device. The voltage generation circuit is configured to generate a voltage difference between the bulk and gate terminals of the MOS device during at least a portion of the ESD event. In this manner, a current handling capability of the MOS device is increased, thereby advantageously enabling a smaller sized device having a significantly smaller capacitance associated therewith to be employed in the ESD protection circuit.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: March 13, 2007
    Assignee: Agere Systems Inc.
    Inventor: Muhammed Ayman Shibib
  • Patent number: 7148540
    Abstract: An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: December 12, 2006
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7126193
    Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: October 24, 2006
    Assignee: Ciclon Semiconductor Device Corp.
    Inventors: Frank A. Baiocchi, Bailey R. Jones, Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7087959
    Abstract: An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A gate is formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions. A first dielectric region is formed in the MOS device, the first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: August 8, 2006
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7067890
    Abstract: A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer such that an insulating layer is formed on at least sidewalls and bottom walls of the trenches. The trenches are configured such that the insulating layer formed as a result of the oxidizing step substantially fills the trenches and substantially consumes the semiconductor layer between corresponding pairs of adjacent trenches. In this manner, a substantially continuous oxide region is formed throughout the plurality of trenches.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 27, 2006
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu