Abstract: Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.

Abstract: Exemplary embodiments of the present invention disclose a modular testing assay. According to various embodiments of the present invention, the sensor arrays, or microplates, are removably attached to a substrate. In some embodiments, the electrical connection between the sensors of the sensor array and the substrate provide for the removal of one sensor array or microplate with another or similar sensor array. The sensor arrays can be aligned using various types of alignment devices or the substrate can be configured to allow various alignments and spatial orientations of one or more sensor arrays.

Abstract: Exemplary embodiments of the present invention disclose a modular testing assay. According to various embodiments of the present invention, the sensor arrays, or microplates, are removably attached to a substrate. In some embodiments, the electrical connection between the sensors of the sensor array and the substrate provide for the removal of one sensor array or microplate with another or similar sensor array. The sensor arrays can be aligned using various types of alignment devices or the substrate can be configured to allow various alignments and spatial orientations of one or more sensor arrays.

Abstract: High performance interconnect devices, structures, and fabrication methods are provided herein. According to some embodiments of the present invention, an interconnect device used to connect components or route signals in an integrated circuit can comprise multiple conductors. A first conductor of the interconnect device can define a first conductor axis, and a second conductor of the interconnect device can define a second conductor axis. The second conductor can be proximate the first conduct such that first conductor axis is substantially coaxially situated relative to the second conductor axis to provide a high performance interconnect having a coaxial alignment. The first conductor and the second conductor can define a gap disposed between and separating the conductors. Other embodiments are also claimed and described.

Abstract: Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.

Abstract: High performance interconnect devices, structures, and fabrication methods are provided herein. According to some embodiments of the present invention, an interconnect device used to connect components or route signals in an integrated circuit can comprise multiple conductors. A first conductor of the interconnect device can define a first conductor axis, and a second conductor of the interconnect device can define a second conductor axis. The second conductor can be proximate the first conduct such that first conductor axis is substantially coaxially situated relative to the second conductor axis to provide a high performance interconnect having a coaxial alignment. The first conductor and the second conductor can define a gap disposed between and separating the conductors. Other embodiments are also claimed and described.

Abstract: Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.

Abstract: Input/output (I/O) interconnects, fluidic I/O interconnects, electrical, optical, and fluidic I/O interconnects, devices incorporating the I/O interconnects, systems incorporating the I/O interconnects, and methods of fabricating the I/O interconnects, devices, and systems, are described herein.

Abstract: Systems and methods for three dimensional lithography, nano-indentation, and combinations thereof are disclosed.

Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.

Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.

Abstract: Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.

Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.

Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.