Patents by Inventor Munehiro Kozuma

Munehiro Kozuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11330213
    Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 10, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda
  • Patent number: 11314484
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: April 26, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takeshi Aoki, Seiichi Yoneda, Yoshiyuki Kurokawa
  • Publication number: 20220085427
    Abstract: A semiconductor device that inhibits deterioration of a secondary battery is provided. The semiconductor device includes a secondary battery module and a first circuit. The secondary battery module includes a secondary battery and a sensor. The first circuit includes a variable resistor. The sensor has a function of measuring a temperature of the secondary battery. The first circuit has a function of judging the charge voltage of the secondary battery and outputting a first result; a function of judging the temperature of the secondary battery measured by the sensor and outputting a second result; a function of determining the magnitude of the variable resistor on the basis of the first result and the second result; a function of discharging the charge voltage through the variable resistor; and a function of stopping discharge when the charge voltage reaches a specified voltage.
    Type: Application
    Filed: January 6, 2020
    Publication date: March 17, 2022
    Inventors: Ryota TAJIMA, Kei TAKAHASHI, Hiroki INOUE, Munehiro KOZUMA, Takahiro FUKUTOME
  • Publication number: 20220077705
    Abstract: A secondary battery deteriorates due to repeated charging and discharging, which leads to a decrease in a battery voltage and a battery capacity. The lifetime of a secondary battery is prolonged by preventing charging at an excessive charging value that would be caused by deterioration of the secondary battery. By performing charge control in consideration of the degree of deterioration of a secondary battery, a longer lifetime of a secondary battery can be achieved. In charging a secondary battery, a charge control circuit controls a current value to a preset value, and a charging current control circuit (specifically a circuit including an error amplifier) included in a protection circuit determines a current value supplied to the secondary battery. That is, the current value supplied to the secondary battery is controlled by both the charge control circuit and the charging current control circuit that is a part of the protection circuit.
    Type: Application
    Filed: December 18, 2019
    Publication date: March 10, 2022
    Inventors: Kei TAKAHASHI, Takayuki IKEDA, Munehiro KOZUMA, Takanori MATSUZAKI, Takahiko ISHIZU, Takeshi AOKI
  • Publication number: 20220052541
    Abstract: Rapid degradation an off-leakage current in an overdischarged state is prevented. In order to prevent an overdischarged state, a control circuit with low leakage current includes a transistor using an oxide semiconductor, whereby the characteristics of the secondary battery are retained. In addition, a system in which a control signal generation circuit is also integrated is formed. With this system structure, the control circuit enters a low-power consumption mode in accordance with the circuit operation after an overdischarge is detected. When recovering from an overdischarged state, the control circuit enters a normally-operating mode in accordance with the voltage increase when charging is started.
    Type: Application
    Filed: December 5, 2019
    Publication date: February 17, 2022
    Inventors: Munehiro KOZUMA, Takayuki IKEDA
  • Publication number: 20220052387
    Abstract: A semiconductor device that detects deterioration of a secondary battery is provided. The semiconductor device includes a power gauge, an anomalous current detection circuit, and a control circuit. The power gauge includes a current divider circuit and an integrator circuit. The anomalous current detection circuit includes a first memory, a second memory, and a first comparator. The integrator circuit can convert a detection current detected at the current divider circuit into a detection voltage by integrating the detection current. The anomalous current detection circuit is supplied with the detection voltage, a first signal at a first time, and a second signal at a second time. The first signal can make the detection voltage at the first time be stored in the first memory and the second signal can make the detection voltage at the second time be stored in the second memory.
    Type: Application
    Filed: December 13, 2019
    Publication date: February 17, 2022
    Inventors: Kei TAKAHASHI, Takayuki IKEDA, Ryota TAJIMA, Mayumi MIKAMI, Yohei MOMMA, Munehiro KOZUMA, Takanori MATSUZAKI
  • Publication number: 20220052535
    Abstract: A battery protection circuit with a novel configuration and a power storage device including the battery protection circuit are provided. The battery protection circuit includes a switch circuit for controlling charge and discharge of a battery cell; the switch circuit includes a mechanical relay, a first transistor, and a second transistor; the switch circuit has a function of controlling electrical connection between a first terminal and a second terminal; the mechanical relay has a function of breaking electrical connection between the first terminal and the second terminal; the first transistor has a function of supplying first current between the first terminal and the second terminal; the second transistor has a function of supplying second current between the first terminal and the second terminal; and the first current is higher than the second current.
    Type: Application
    Filed: November 6, 2019
    Publication date: February 17, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Takayuki IKEDA, Munehiro KOZUMA, Takanori MATSUZAKI, Akio SUZUKI, Seiya SAITO
  • Publication number: 20220045683
    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.
    Type: Application
    Filed: December 10, 2019
    Publication date: February 10, 2022
    Inventors: Hiroki INOUE, Munehiro KOZUMA, Takeshi AOKI, Shuji FUKAI, Fumika AKASAWA, Shintaro HARADA, Sho NAGAO
  • Publication number: 20220020793
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Publication number: 20210391604
    Abstract: A novel semiconductor device that is highly convenient or reliable is provided. The semiconductor device includes a sensor unit, a first memory unit, a second memory unit, and a determination unit. The sensor unit supplies a sensor signal, the first memory unit retains the sensor signal, the second memory unit retains standard data and allowable difference information, the determination unit compares the sensor signal with the standard data, and the determination unit supplies a control signal in the case where a difference between the sensor signal and the standard data exceeds the allowable difference information.
    Type: Application
    Filed: November 13, 2019
    Publication date: December 16, 2021
    Inventors: Takanori MATSUZAKI, Takayuki IKEDA, Munehiro KOZUMA, Ryota TAJIMA, Hiroki INOUE
  • Publication number: 20210384751
    Abstract: A battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including either of the battery circuits are provided. The power storage device includes a first circuit portion, a second circuit portion, a third circuit portion, and a secondary battery; the first circuit portion has a function of controlling charging of the secondary battery; the first circuit portion has a function of supplying the start time and the end time of the charging of the secondary battery to the third circuit portion; the second circuit portion has functions of generating a first voltage and a first current and supplying them to the third circuit portion; the third circuit portion has a function of generating a second voltage by charging the first current in a capacitor; and the third circuit portion has a function of comparing the first voltage and the second voltage.
    Type: Application
    Filed: October 16, 2019
    Publication date: December 9, 2021
    Inventors: Kei TAKAHASHI, Takayuki IKEDA, Takanori MATSUZAKI, Munehiro KOZUMA, Hiroki INOUE, Ryota TAJIMA, Yohei MOMMA, Mayumi MIKAMI, Kazutaka KURIKI, Shunpei YAMAZAKI
  • Publication number: 20210384753
    Abstract: The safety is ensured in such a manner that with an abnormality detection system of a secondary battery, abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early, and a user is warned or the use of the secondary battery is stopped. The abnormality detection system of the secondary battery determines whether the temperature of the secondary battery is within a temperature range in which normal operation can be performed on the basis of temperature data obtained with a temperature sensor. In the case where the temperature of the secondary battery is high, a cooling device is driven by a control signal from the abnormality detection system of the secondary battery. The abnormality detection system of the secondary battery includes at least a memory means. The memory means has a function of holding an analog signal and includes a transistor using an oxide semiconductor for a semiconductor layer.
    Type: Application
    Filed: October 15, 2019
    Publication date: December 9, 2021
    Inventors: Munehiro KOZUMA, Takayuki IKEDA, Takanori MATSUZAKI, Kei TAKAHASHI, Mayumi MIKAMI, Shunpei YAMAZAKI
  • Patent number: 11139327
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 5, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Publication number: 20210249703
    Abstract: A semiconductor device capable of charging that is less likely to cause deterioration of a power storage device is provided. The amount of a charging current is adjusted in accordance with the ambient temperature. Charging under low-temperature environments is performed with a reduced charging current. When the ambient temperature is too low or too high, the charging is stopped. Measurement of the ambient temperature is performed with a memory element using an oxide semiconductor. The use of a memory element using an oxide semiconductor enables measurement of the ambient temperature and retention of the temperature information to be performed at the same time.
    Type: Application
    Filed: July 3, 2019
    Publication date: August 12, 2021
    Inventors: Takayuki IKEDA, Munehiro KOZUMA, Takanori MATSUZAKI, Ryota TAJIMA, Shunpei YAMAZAKI
  • Publication number: 20210126473
    Abstract: Safety is secured in such a manner that an anomaly of a secondary battery is detected with a protection circuit, for example, a phenomenon that lowers the safety of a secondary battery, particularly a micro short circuit, is detected early, and users are warned or the use of the secondary battery is stopped. A secondary battery protection circuit includes a first memory circuit electrically connected to a secondary battery, a comparison circuit electrically connected to the first memory circuit, a second memory circuit electrically connected to the comparison circuit, and a power-off switch electrically connected to the second memory circuit. The power-off switch is electrically connected to the secondary battery, and the first memory circuit includes a first transistor including an oxide semiconductor and retains a voltage value of the secondary battery in an analog manner.
    Type: Application
    Filed: June 27, 2019
    Publication date: April 29, 2021
    Inventors: Takayuki IKEDA, Munehiro KOZUMA, Takanori MATSUZAKI, Ryota TAJIMA, Shunpei YAMAZAKI, Yuki OKAMOTO
  • Publication number: 20200343245
    Abstract: Provided is a storage device that achieves both retention operation at high temperatures and high-speed operation at low temperatures. The storage device includes a driver circuit and a plurality of memory cells, and the memory cell includes a transistor and a capacitor; the transistor includes a metal oxide in a channel formation region. In the case where the transistor includes a first gate and a second gate, the driver circuit has a function of driving the second gate, and the driver circuit outputs a potential corresponding to the temperature of the storage device or the temperature of an environment where the storage device is placed to the second gate in a period during which the memory cell retains data.
    Type: Application
    Filed: November 22, 2018
    Publication date: October 29, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Munehiro KOZUMA, Takeshi AOKI, Hiroki INOUE, Shintaro HARADA, Daisuke MATSUBAYASHI
  • Publication number: 20200201603
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Application
    Filed: May 7, 2018
    Publication date: June 25, 2020
    Inventors: Munehiro KOZUMA, Takeshi AOKI, Seiichi YONEDA, Yoshiyuki KUROKAWA
  • Patent number: 10686080
    Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Publication number: 20200160158
    Abstract: A neural network circuit having a novel structure is provided. A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.
    Type: Application
    Filed: April 2, 2018
    Publication date: May 21, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki OKAMOTO, Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA
  • Publication number: 20200154068
    Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.
    Type: Application
    Filed: December 16, 2019
    Publication date: May 14, 2020
    Inventors: Takashi NAKAGAWA, Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA