Patents by Inventor Munehiro Kozuma

Munehiro Kozuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009688
    Abstract: The safety is ensured in such a manner that with an abnormality detection system of a secondary battery, abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early, and a user is warned or the use of the secondary battery is stopped. The abnormality detection system of the secondary battery determines whether the temperature of the secondary battery is within a temperature range in which normal operation can be performed on the basis of temperature data obtained with a temperature sensor. In the case where the temperature of the secondary battery is high, a cooling device is driven by a control signal from the abnormality detection system of the secondary battery. The abnormality detection system of the secondary battery includes at least a memory means. The memory means has a function of holding an analog signal and includes a transistor using an oxide semiconductor for a semiconductor layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 11, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Takanori Matsuzaki, Kei Takahashi, Mayumi Mikami, Shunpei Yamazaki
  • Patent number: 12002535
    Abstract: A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: June 4, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Munehiro Kozuma, Masashi Fujita, Takahiko Ishizu
  • Publication number: 20240179987
    Abstract: A display apparatus with a driver circuit having redundancy is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a first driver circuit and a second driver circuit. The second layer includes a first pixel region and a second pixel region. The first pixel region includes a first pixel circuit and the second pixel region includes a second pixel circuit. The first pixel region includes a region overlapping with the first circuit and the second pixel region includes a region overlapping with the second circuit. The first pixel circuit is electrically connected to the first driver circuit through a first wiring, the second pixel circuit is electrically connected to the second driver circuit through a second wiring, and the first wiring is electrically connected to the second wiring through a switch.
    Type: Application
    Filed: March 18, 2022
    Publication date: May 30, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Minato ITO, Munehiro KOZUMA, Yuki OKAMOTO, Yusuke KOUMURA
  • Patent number: 11996133
    Abstract: Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 28, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumika Akasawa, Munehiro Kozuma
  • Patent number: 11988720
    Abstract: A semiconductor device that detects deterioration of a secondary battery is provided. The semiconductor device includes a power gauge, an anomalous current detection circuit, and a control circuit. The power gauge includes a current divider circuit and an integrator circuit. The anomalous current detection circuit includes a first memory, a second memory, and a first comparator. The integrator circuit can convert a detection current detected at the current divider circuit into a detection voltage by integrating the detection current. The anomalous current detection circuit is supplied with the detection voltage, a first signal at a first time, and a second signal at a second time. The first signal can make the detection voltage at the first time be stored in the first memory and the second signal can make the detection voltage at the second time be stored in the second memory.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 21, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Takayuki Ikeda, Ryota Tajima, Mayumi Mikami, Yohei Momma, Munehiro Kozuma, Takanori Matsuzaki
  • Patent number: 11990778
    Abstract: Safety is secured in such a manner that an anomaly of a secondary battery is detected with a protection circuit, for example, a phenomenon that lowers the safety of a secondary battery, particularly a micro short circuit, is detected early, and users are warned or the use of the secondary battery is stopped. A secondary battery protection circuit includes a first memory circuit electrically connected to a secondary battery, a comparison circuit electrically connected to the first memory circuit, a second memory circuit electrically connected to the comparison circuit, and a power-off switch electrically connected to the second memory circuit. The power-off switch is electrically connected to the secondary battery, and the first memory circuit includes a first transistor including an oxide semiconductor and retains a voltage value of the secondary battery in an analog manner.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 21, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Munehiro Kozuma, Takanori Matsuzaki, Ryota Tajima, Shunpei Yamazaki, Yuki Okamoto
  • Publication number: 20240161695
    Abstract: A display apparatus with a novel structure is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a driver circuit region, and the second layer includes a pixel array. The pixel array includes a plurality of pixel regions. The driver circuit region includes a control circuit unit and a plurality of local driver circuits. One of the plurality of local driver circuits corresponds to any one of the plurality of pixel regions. The local driver circuit has a function of outputting a driving signal for driving a plurality of pixels included in the corresponding pixel region.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 16, 2024
    Inventors: Minato ITO, Takanori MATSUZAKI, Munehiro KOZUMA, Yuki OKAMOTO, Yusuke KOUMURA
  • Patent number: 11961979
    Abstract: A semiconductor device capable of charging that is less likely to cause deterioration of a power storage device is provided. The amount of a charging current is adjusted in accordance with the ambient temperature. Charging under low-temperature environments is performed with a reduced charging current. When the ambient temperature is too low or too high, the charging is stopped. Measurement of the ambient temperature is performed with a memory element using an oxide semiconductor. The use of a memory element using an oxide semiconductor enables measurement of the ambient temperature and retention of the temperature information to be performed at the same time.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Munehiro Kozuma, Takanori Matsuzaki, Ryota Tajima, Shunpei Yamazaki
  • Publication number: 20240090284
    Abstract: A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings.
    Type: Application
    Filed: January 17, 2022
    Publication date: March 14, 2024
    Inventors: Munehiro KOZUMA, Tatsuya ONUKI, Takayuki IKEDA, Takanori MATSUZAKI
  • Patent number: 11923707
    Abstract: A battery protection circuit with a novel configuration and a power storage device including the battery protection circuit are provided. The battery protection circuit includes a switch circuit for controlling charge and discharge of a battery cell; the switch circuit includes a mechanical relay, a first transistor, and a second transistor; the switch circuit has a function of controlling electrical connection between a first terminal and a second terminal; the mechanical relay has a function of breaking electrical connection between the first terminal and the second terminal; the first transistor has a function of supplying first current between the first terminal and the second terminal; the second transistor has a function of supplying second current between the first terminal and the second terminal; and the first current is higher than the second current.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda, Munehiro Kozuma, Takanori Matsuzaki, Akio Suzuki, Seiya Saito
  • Patent number: 11908947
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 20, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takahiko Ishizu, Takeshi Aoki, Masashi Fujita, Kazuma Furutani, Kousuke Sasaki
  • Patent number: 11875837
    Abstract: A semiconductor device resistant to a high temperature with low power consumption is provided. The semiconductor device includes a first and a second circuit, a first and a second cell, and a first and a second wiring. The first cell includes a first transistor, and the second cell includes a second transistor. The first and the second transistor operate in a subthreshold region. The first cell is electrically connected to the first circuit through the first wiring, the first cell is electrically connected to the second circuit through the second wiring, and the second cell is electrically connected to the second circuit through the second wiring. The first cell sets a current flowing through the first transistor to a first current and the second cell sets a current flowing through the second transistor to a second current. At this time, a potential corresponding to the second current is input from the second wiring to the first cell.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: January 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Munehiro Kozuma, Takeshi Aoki
  • Publication number: 20230352477
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. The analog calculator, the first memory circuit, and the second memory circuit each include a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data to the digital calculator as digital data. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data to the analog calculator as analog data. The analog calculator has a function of performing product-sum operation using the second weight data.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 2, 2023
    Inventors: Takanori MATSUZAKI, Tatsuya ONUKI, Munehiro KOZUMA, Takeshi AOKI, Yuki OKAMOTO, Takayuki IKEDA
  • Publication number: 20230352502
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 2, 2023
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Patent number: 11799430
    Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 24, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Takeshi Aoki, Munehiro Kozuma, Takayuki Ikeda
  • Patent number: 11791640
    Abstract: Rapid degradation an off-leakage current in an overdischarged state is prevented. In order to prevent an overdischarged state, a control circuit with low leakage current includes a transistor using an oxide semiconductor, whereby the characteristics of the secondary battery are retained. In addition, a system in which a control signal generation circuit is also integrated is formed. With this system structure, the control circuit enters a low-power consumption mode in accordance with the circuit operation after an overdischarge is detected. When recovering from an overdischarged state, the control circuit enters a normally-operating mode in accordance with the voltage increase when charging is started.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 17, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takayuki Ikeda
  • Publication number: 20230326491
    Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell.
    Type: Application
    Filed: May 6, 2021
    Publication date: October 12, 2023
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA, Tatsunori INOUE
  • Patent number: 11777502
    Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 3, 2023
    Inventors: Hiroki Inoue, Munehiro Kozuma, Takeshi Aoki, Shuji Fukai, Fumika Akasawa, Sho Nagao
  • Publication number: 20230297339
    Abstract: A semiconductor device with a novel structure is provided. A first memory circuit portion includes a first memory circuit for retaining a plurality of pieces of first weight data. A second memory circuit portion includes a second memory circuit for retaining a plurality of pieces of second weight data. A first arithmetic circuit portion includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit portion includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit has a function of supplying any one of the plurality of pieces of the first weight data to a first wiring. The second switching circuit has a function of supplying any one of the plurality of pieces of the second weight data to a second wiring.
    Type: Application
    Filed: July 5, 2021
    Publication date: September 21, 2023
    Inventors: Yuki OKAMOTO, Minato ITO, Munehiro KOZUMA
  • Patent number: 11710751
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 25, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki