Patents by Inventor Munehiro Kozuma
Munehiro Kozuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200201603Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.Type: ApplicationFiled: May 7, 2018Publication date: June 25, 2020Inventors: Munehiro KOZUMA, Takeshi AOKI, Seiichi YONEDA, Yoshiyuki KUROKAWA
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Patent number: 10686080Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.Type: GrantFiled: April 4, 2019Date of Patent: June 16, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Nakagawa, Yoshiyuki Kurokawa, Munehiro Kozuma
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Publication number: 20200160158Abstract: A neural network circuit having a novel structure is provided. A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.Type: ApplicationFiled: April 2, 2018Publication date: May 21, 2020Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki OKAMOTO, Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA
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Publication number: 20200154068Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.Type: ApplicationFiled: December 16, 2019Publication date: May 14, 2020Inventors: Takashi NAKAGAWA, Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA
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Publication number: 20200035726Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.Type: ApplicationFiled: October 3, 2019Publication date: January 30, 2020Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
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Patent number: 10540944Abstract: A small semiconductor device is provided. The semiconductor device includes a register, switches, a memory circuit, a controller, and a display. An output terminal of the register is electrically connected to two or more of the switches. The switches are electrically connected to the memory circuit. The register has a function of retaining data corresponding to a parameter used when the controller operates. The switches have a function of selecting the memory circuit to which the data retained in the register is to be output. The memory circuit has a function of retaining the data output from the register. The controller has a function of reading the data retained in the memory circuit to control operation of the display.Type: GrantFiled: September 20, 2017Date of Patent: January 21, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Munehiro Kozuma
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Patent number: 10536657Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.Type: GrantFiled: March 9, 2017Date of Patent: January 14, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda
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Patent number: 10535691Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.Type: GrantFiled: June 9, 2016Date of Patent: January 14, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
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Patent number: 10504919Abstract: To achieve high processing capability, a semiconductor device includes first and second circuits, first to third wirings, and first to fourth transistors. The first circuit is electrically connected to the first wiring and a gate of the first transistor. One of a source and a drain of the first transistor is electrically connected to the second wiring. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. The second circuit is electrically connected to the first wiring and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to the third wiring. The other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor. One of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor.Type: GrantFiled: October 25, 2016Date of Patent: December 10, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa
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Patent number: 10390075Abstract: A semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder. The decoder includes a first circuit. The first circuit is configured to operate in synchronization with a clock signal. The first circuit is configured to perform image processing. A circuit configuration of the first circuit can be changed. Clock gating is performed on the first circuit to prevent the clock signal from being input to the first circuit when the circuit configuration of the first circuit is being changed. A broadcasting system including the semiconductor device is also provided.Type: GrantFiled: October 10, 2017Date of Patent: August 20, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Munehiro Kozuma
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Publication number: 20190229216Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.Type: ApplicationFiled: April 4, 2019Publication date: July 25, 2019Inventors: Takashi NAKAGAWA, Yoshiyuki KUROKAWA, Munehiro KOZUMA
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Patent number: 10263119Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.Type: GrantFiled: September 7, 2017Date of Patent: April 16, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Nakagawa, Yoshiyuki Kurokawa, Munehiro Kozuma
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Publication number: 20190096206Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.Type: ApplicationFiled: March 9, 2017Publication date: March 28, 2019Inventors: Takashi NAKAGAWA, Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA
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Patent number: 10230368Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.Type: GrantFiled: June 24, 2016Date of Patent: March 12, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Takeshi Aoki
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Patent number: 10216999Abstract: A display system is provided. The display system includes an imaging device, a processing device, and a display device that includes first and second display elements. The imaging device has a function of supplying imaging data based on a captured image. The processing device has a function of receiving the imaging data, supplying first image data containing at least part of the captured image, performing determination processing for determining whether the captured image contains a predetermined object, performing image processing based on the result of the determination processing, and supplying second image data based on the image processing. The display device has a function of receiving the first and second image data. The first display element has a function of displaying an image based on the first image data, and the second display element has a function of displaying an image based on the second image data.Type: GrantFiled: September 13, 2017Date of Patent: February 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa
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Patent number: 10177767Abstract: A semiconductor device includes a configuration memory that has functions of holding configuration data and generating a signal based on the configuration data, a context generator that has a function of generating a signal for controlling context switch, a clock generator that has a function of operating in a first mode or a second mode in accordance with the signal generated in the configuration memory, and a PLD. A clock signal is input to the context generator and the clock generator. The clock generator outputs the clock signal to the PLD in the first mode and stops outputting the clock signal to the PLD in the second mode.Type: GrantFiled: November 8, 2016Date of Patent: January 8, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Munehiro Kozuma
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Patent number: 10141054Abstract: A semiconductor device that has a long data retention time during stop of supply of power supply voltage by reducing leakage current due to miniaturization of a semiconductor element. In a structure where charge corresponding to data is held with the use of low off-state current of a transistor containing an oxide semiconductor in its channel formation region, a transistor for reading data and a transistor for storing charge are separately provided, thereby decreasing leakage current flowing through a gate insulating film.Type: GrantFiled: August 9, 2016Date of Patent: November 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeshi Aoki, Munehiro Kozuma, Yoshiyuki Kurokawa
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Patent number: 10027324Abstract: Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured.Type: GrantFiled: March 28, 2017Date of Patent: July 17, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa
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Patent number: 10002656Abstract: A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.Type: GrantFiled: April 26, 2016Date of Patent: June 19, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa, Munehiro Kozuma
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Patent number: 9998119Abstract: Provided is a semiconductor device in which leakage current due to miniaturization of a semiconductor element is reduced and delay at a time of context switch of a multi-context PLD is reduced. A first transistor and a second transistor included in a charge retention circuit functioning as a configuration memory each include an oxide semiconductor in a semiconductor layer serving as a channel formation region. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is connected to a switch for context switch. In the switch used for context switch, electrostatic capacitance on an input side to which the one of the source and the drain of the second transistor is connected is larger than electrostatic capacitance on an output side.Type: GrantFiled: May 12, 2017Date of Patent: June 12, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shintaro Harada, Munehiro Kozuma, Yoshiyuki Kurokawa