Patents by Inventor Munehiro Uratani

Munehiro Uratani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7529528
    Abstract: A power consumption controlling apparatus controls power consumption of a high frequency amplifier to reduce the power consumption by adjusting a power supply voltage and a bias voltage of the high frequency amplifier which amplifies a high frequency transmitting signal. The power consumption controlling apparatus includes: a receiving circuit for receiving the high frequency transmitting signal amplified by the high frequency amplifier; an evaluating section for evaluating whether or not a receiving signal obtained from the receiving circuit satisfies a predetermined quality; and an adjusting section for adjusting the power supply voltage and the bias voltage in a range in which the receiving signal evaluated by the evaluating section satisfies the predetermined quality.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: May 5, 2009
    Assignees: Sharp Kabushiki Kaisha, National Institute of Advanced Industrial Science and Technology
    Inventors: Munehiro Uratani, Yuji Kasai, Tetsuya Higuchi, Eiichi Takahashi
  • Patent number: 7447289
    Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: November 4, 2008
    Assignees: Sharp Kabushiki Kaisha, National Institute of Advanced Industrial Science and Technology
    Inventors: Munehiro Uratani, Eiichi Takahashi, Yuji Kasai, Tetsuya Higuchi, Masahiro Murakawa
  • Patent number: 7248095
    Abstract: A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: July 24, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Munehiro Uratani, Yuji Kasai, Tetsuya Higuchi, Eiichi Takahashi
  • Publication number: 20060055449
    Abstract: A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 16, 2006
    Inventors: Munehiro Uratani, Yuji Kasai, Tetsuya Higuchi, Eiichi Takahashi
  • Publication number: 20060046668
    Abstract: A power consumption controlling apparatus controls power consumption of a high frequency amplifier to reduce the power consumption by adjusting a power supply voltage and a bias voltage of the high frequency amplifier which amplifies a high frequency transmitting signal. The power consumption controlling apparatus includes: a receiving circuit for receiving the high frequency transmitting signal amplified by the high frequency amplifier; an evaluating section for evaluating whether or not a receiving signal obtained from the receiving circuit satisfies a predetermined quality; and an adjusting section for adjusting the power supply voltage and the bias voltage in a range in which the receiving signal evaluated by the evaluating section satisfies the predetermined quality.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 2, 2006
    Inventors: Munehiro Uratani, Yuji Kasai, Tetsuya Higuchi, Eiichi Takahashi
  • Publication number: 20040190665
    Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 30, 2004
    Inventors: Munehiro Uratani, Eiichi Takahashi, Yuji Kasai, Tetsuya Higuchi, Masahiro Murakawa
  • Patent number: 6546542
    Abstract: A method of designing a data driven information processor employing self-timed pipeline control includes the steps of preparing a computer-readable library file in which is written designing parameters related to a functional block and processor of an apparatus that is the subject of design, setting a parameter value for each designing parameter according to a design specification, and executing on a computer a tool that rewrites each description of the parameter in the library file using a set parameter value and producing a register transfer level design description.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: April 8, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Manabu Yumoto, Munehiro Uratani
  • Publication number: 20020023250
    Abstract: A method of designing a data driven information processor employing self-timed pipeline control includes the steps of preparing a computer-readable library file in which is written designing parameters related to a functional block and processor of an apparatus that is the subject of design, setting a parameter value for each designing parameter according to a design specification, and executing on a computer a tool that rewrites each description of the parameter in the library file using a set parameter value and producing a register transfer level design description.
    Type: Application
    Filed: June 8, 2001
    Publication date: February 21, 2002
    Inventors: Manabu Yumoto, Munehiro Uratani
  • Patent number: 5610850
    Abstract: The absolute difference calculation circuits 101 through 10N each consisting of a subtractor which calculates the difference of two numbers each consisting of i bits and a bit inversion selector circuit which-provides the result of subtraction as it is when no borrow output is produced by the subtractor, and inverts every bit of the result of subtraction when there is a borrow output, to obtain 1's complement of the absolute value of difference. The multiple input adder 2 receives the borrow as input to the least significant bit thereof and adds the result of each absolute difference calculation circuit. Because the adding operations to obtain 2's complement in the absolute difference calculation circuit are carried out together in the multiple input adder that follows, number of adders required to calculate the absolute value of difference can be greatly reduced and the amount of entire circuitry can be greatly reduced.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: March 11, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Munehiro Uratani, Aoi Kitaura
  • Patent number: 5353251
    Abstract: A memory cell circuit for a CMOS static RAM is provided, which includes a latch portion for holding logic high or logic low data depending on the potential of a single bit line, and a transfer gate having a first terminal connected to the latch portion and a second terminal connected to the single bit line, the transfer gate electrically connecting or disconnecting the first and second terminals in response to a selection signal, wherein the transfer gate includes a first transistor and a second transistor connected in parallel between the first and second terminals, both of the first and second transistors being activated at a data write operation, while one of the first and second transistors being activated at a data read operation.
    Type: Grant
    Filed: September 16, 1993
    Date of Patent: October 4, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Munehiro Uratani, Aoi Kitaura
  • Patent number: 4783692
    Abstract: A semiconductor device in a CMOS gate array in which a basic cell has inputs by the number of n, wherein the basic cell comprises 2n PMOS transistors and 2r NMOS transistors is disclosed. The basic cell comprises, in a same basic cell, MOS transistors having at least two gate electrodes connected in common and MOS transistors operated on one gate electrode, and a logic circuit is formed by transistors of different gate width.
    Type: Grant
    Filed: April 28, 1986
    Date of Patent: November 8, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Munehiro Uratani
  • Patent number: 4684829
    Abstract: A semi-conductor decoder circuit includes 2.sup.N-1 circuits each formed of transistors vertically arranged in N stages, with the transistors of 2.sup.N-1, 2.sup.N-2 . . . 2.sup.1, 2.sup.0 number being disposed sequentially from the output stage in N stages in a tree structure. The gate width of the transistor at each stage is expanded as a distance from the output stage is increased so as to prevent an increase in ON resistance of the circuit and also to achieve a high speed operation.
    Type: Grant
    Filed: July 10, 1984
    Date of Patent: August 4, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Munehiro Uratani
  • Patent number: 4453236
    Abstract: An integrated circuit comprises a memory array containing a plurality of memory cells arranged in a matrix shape having rows and columns, and memory array addressing circuitry for addressing such array in accordance with addressing signals. Said addressing circuitry comprises a number of gates responsive to addressing signals for addressing the array. Only one of the number of gates has a control signal applied thereto which places the memory array in such a condition that none of the memory cells is selected for addressing purposes, and the remaining gates do not have a control signal applied even under the same situation, wherein none of the memory cells is selected for addressing purposes. The gates comprise an AND gate, an NAND gate, an NOR gate or the like.
    Type: Grant
    Filed: April 18, 1980
    Date of Patent: June 5, 1984
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Munehiro Uratani, Setsufumi Kamuro