Patents by Inventor Murali Subramanian

Murali Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11537314
    Abstract: Systems and methods are provided for bringing a volume of a consistency group (CG) into an in-synchronization (InSync) state while other volumes of the CG remain in the InSync state. According to an example, in order to support recovery from disruptive events in a manner that ensures a zero recovery point objective (RPO) guarantee and insulates an application making use of the CG from adverse impacts, responsive to a triggering event, a Fast Resync process may first be attempted to promptly bring an affected volume back into an in-synchronization (InSync) state from an out of synchronization (OOS) state while allowing other members of the CG to remain in the InSync state. Should the Fast resync process be unsuccessful in bringing the volume back into the InSync state within a predetermined or configurable time threshold, then a second type of resynchronization process may be employed at the CG level.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: December 27, 2022
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Akhil Kaushik, Anoop Vijayan, Arun Kumar Selvam
  • Publication number: 20220317897
    Abstract: Systems and methods are described for efficiently performing various operations at the granularity of a consistency group (CG) within a cross-site storage solution. An example of one of the various operations includes an independent and parallel resynchronization approach that independently brings individual volumes of a CG to a steady state of in-synchronization (InSync), thereby contributing to scalability of CGs by supporting CGs having a large number of member volumes without requiring a change to the resynchronization process. Another example includes preserving dependent write-order consistency when a remote mirror copy goes out-of-synchronization (OOS) for any reason by driving all member volumes OOS responsive to any member volume becoming OOS. Yet another example includes independent creation of snapshots by member volumes to support efficient and on-demand creation by an application of a common snapshots of all or a subset of peered member volumes of a CG with which the application is associated.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: MURALI SUBRAMANIAN, Akhil Kaushik, Anoop Vijayan, Omprakash Khandelwal, Arun Kumar Selvam
  • Publication number: 20220318105
    Abstract: Systems and methods for re-aligning data replication configuration of a cross-site storage solution after a failover are provided. According to one embodiment, after a failover, the new primary distributed storage system orchestrates flipping of the data replication configuration of a peered consistency group (CG) to reestablish zero RPO and zero RTO protections for the peered CG. The primary causes the secondary distributed storage system to perform an atomic database operation on its remote configuration database to (i) delete an existing source configuration that identifies the secondary as a source of data replication; and (ii) persist a new destination configuration identifying the secondary as a destination of data replication.
    Type: Application
    Filed: May 23, 2022
    Publication date: October 6, 2022
    Inventors: Murali Subramanian, Sohan SHETTY, Akhil Kaushik
  • Publication number: 20220292808
    Abstract: Method and system for identifying an empty region in a label and placing a content thereon is provided. The method includes processing an image of the label to extract label attribute and the content to retrieve content attribute. Label attribute includes at least one of dimensions of the label, at least one pre-existing content on the label, dimensions associated with pre-existing content, and location of pre-existing content on the label. The content attribute includes a type of content, dimensions of content, a preferred label location associated with content. The method further includes determining at least one empty region within the label, based on extracted label attribute and the retrieved content attribute. Each of the at least one empty region may be configured to accommodate the content. The method further includes inserting the content into one of the at least one empty region based on a predefined rule.
    Type: Application
    Filed: February 25, 2022
    Publication date: September 15, 2022
    Inventors: HARIPRASATH J, NAVEEN SUBRAMANIAN, MURALI KRISHNAAN GAJAPATHY, YUVARAJAN SHANMUGASUNDARAM, NISHAR AHAMED
  • Patent number: 11360867
    Abstract: Systems and methods for re-aligning data replication configuration of a cross-site storage solution after a failover are provided. According to one embodiment, after a failover, the new primary distributed storage system orchestrates flipping of the data replication configuration of a peered consistency group (CG) to reestablish zero RPO and zero RTO protections for the peered CG. The primary causes the secondary distributed storage system to perform an atomic database operation on its remote configuration database to (i) delete an existing source configuration that identifies the secondary as a source of data replication; and (ii) persist a new destination configuration identifying the secondary as a destination of data replication.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 14, 2022
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Sohan Shetty, Akhil Kaushik
  • Publication number: 20180291605
    Abstract: Disclosure provides mechanical odor trap mechanism that can be coupled anywhere in the plumbing of a urinal system below the operative base. A receptacle is provided to receive and discharge the fluid from the urinal via a floatation device that is configured to float in the presence of fluid and settle down into the discharge opening in the absence of fluid to sealingly close the opening and block the escape of odor. A self cleaning urinal system can be configured to implement such mechanical odor trap mechanism and further be configured with spraying mechanism disposed at an elevation to spray water and/or air jets to wash away splattered fluid residue. A feces, urine and wash water separating toilet pan can be provided with a lid configured to sealingly close the opening for feces to enable washing without the user shifting positions and also to block odor.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 11, 2018
    Inventor: Krupakar Murali Subramanian
  • Patent number: 9679781
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 9219740
    Abstract: Certain embodiments of the invention relate to an access control system defining one or more compartments and providing rules, which are applied to the compartment(s), to control access to network services by entities that are associated with a said compartment, the rules comprising at least a first kind of rule for controlling access to network services that use dynamically-assigned communications ports.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 22, 2015
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Murali Subramanian, Anantha Keerthi Banavara Ramaswamy, Arun Keshava Murthy
  • Publication number: 20150318149
    Abstract: Systems and methods for high pressure plasma discharge, wherein a system comprises at least one electrode which is fragmented into pieces and arranged to form a fragmented electrode system; at least one dielectric material placed between or parallel to the at least one electrode and another second electrode or fragmented pieces of the fragmented electrode systems, wherein the at least one electrode or fragmented pieces of the fragmented electrode system may have same or opposite charge; and at least one power supply unit; wherein the pieces of the electrode which is fragmented can be arranged parallel or divergent or convergent to one another and are at an angle to each other or the central axis passing through the electrode.
    Type: Application
    Filed: December 11, 2013
    Publication date: November 5, 2015
    Inventor: Krupakar Murali Subramanian
  • Publication number: 20150287610
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 8, 2015
    Inventors: MIRZAFER ABATCHEV, DAVID WELLS, BAOSUO ZHOU, KRUPAKAR MURALI SUBRAMANIAN
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 8747557
    Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Krupakar Murali Subramanian, Neal Rueger, Gurtej Sandhu
  • Patent number: 8719830
    Abstract: A method of producing a compartment specification for an application, the method comprising executing the application; determining resource requests made by the executing application; and recording the resource requests in the compartment specification.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: May 6, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Murali Subramanian, Ratan Prasad Nalumasu, Animesh Singh, Chandrika Malurpatna Sreedhar
  • Publication number: 20130295770
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Application
    Filed: July 5, 2013
    Publication date: November 7, 2013
    Inventors: Mirzafer Abatchev, David Wells, Baosuo ` Zhou, Krupakar Murali Subramanian
  • Patent number: 8359467
    Abstract: Certain embodiments of the invention relate to an access control system for controlling access to file system objects stored in a digital file system store. The system provides a first compartment rule type for granting a first permission to an entity, associated with a respective compartment to which the rule is applied, to lookup a directory object in a directory path and list the contents of the said directory object, and a second compartment rule type for granting a second permission to an entity, associated with a respective compartment to which the rule is applied, to lookup a directory object in a directory path and not to list the contents of the said directory object.
    Type: Grant
    Filed: July 7, 2007
    Date of Patent: January 22, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Murali Subramanian, Animesh Singh, Ratan Prasad Nalumasu, Chandrika Malurpatna Sreedhar
  • Patent number: 7910483
    Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 22, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer K Abatchev, Krupaker Murali Subramanian, Baosuo Zhou
  • Publication number: 20100173498
    Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
    Type: Application
    Filed: February 2, 2010
    Publication date: July 8, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mirzafer K. Abatchev, Krupaker Murali Subramanian, Baosuo Zhou
  • Patent number: 7662718
    Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer K. Abatchev, Krupakar Murali Subramanian, Baosuo Zhou
  • Publication number: 20090308312
    Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.
    Type: Application
    Filed: March 5, 2009
    Publication date: December 17, 2009
    Inventors: Krupakar Murali Subramanian, Neal Rueger, Gurtej Sandhu
  • Publication number: 20090150886
    Abstract: A method of producing a compartment specification for an application, the method comprising executing the application; determining resource requests made by the executing application; and recording the resource requests in the compartment specification.
    Type: Application
    Filed: August 21, 2008
    Publication date: June 11, 2009
    Inventors: Murali Subramanian, Ratan Prasad Nalumasu, Animesh Singh, Chandrika Malurpatna Sreedhar