Patents by Inventor Mustafa Keskin

Mustafa Keskin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12181963
    Abstract: An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: December 31, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yi-Hung Tseng, Marzio Pedrali-Noy, Charles James Persico, Mustafa Keskin
  • Publication number: 20240427683
    Abstract: This disclosure provides methods, devices, and systems for troubleshooting operation of an electronic device, the method comprising by receiving performance data from a plurality of electrical components, and including a portion of the performance data within a dynamic time window. The portion includes event data. The dynamic time window may be manipulated to include dependent event data within the portion. The dependent event data shares an interdependency with the event data. Troubleshooting analysis determined from the interdependency may be output.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Mustafa KESKIN, Murat CAKIR, Lindsey Makana KOSTAS
  • Publication number: 20240419963
    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for distributing a workload across computing devices within a distributed computing system. An example method generally includes receiving, from at least one respective computing device of a plurality of computing devices in a distributed computing environment, information defining a respective power neural network. The respective power neural network generally is trained to predict power utilization for the respective computing device for a task to be executed on the respective computing device. For one or more computing devices, power utilization is predicted for a workload to be executed within the distributed computing environment based on respective power neural networks associated with the one or more computing devices. Instructions to execute at least a portion of the workload based on the predicted power utilizations for the one or more computing devices are transmitted to the plurality of computing devices.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 19, 2024
    Inventors: Mustafa KESKIN, Shruti CHITTAWADGI, Omprakash GUNIYA MOHAN RAM, Christopher KOOB, Andriy TEMKO, Venkatarakesh Kumar MAMIDI
  • Publication number: 20240394930
    Abstract: In some aspects, a user equipment (UE) may identify a boundary for interacting with content. The UE may determine a center of gravity within the boundary for interacting with the content. The UE may modify the content in accordance with the center of gravity. Numerous other aspects are described.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Inventor: Mustafa KESKIN
  • Publication number: 20240316459
    Abstract: In some aspects, a user equipment (UE) may display content via a display associated with the UE. The UE may receive an input via a sensor associated with the UE while displaying the content. The UE may alter the content based at least in part on the input, wherein altering the content comprises introducing a character into the content or changing an environment or a difficulty of the content. Numerous other aspects are described.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Inventor: Mustafa KESKIN
  • Publication number: 20240311622
    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for operating a neural network using one or more selectable activation functions. The method generally includes generating an intermediate output of a neural network for an input into the neural network. One or more activation functions to apply to the intermediate output are selected. An output of the neural network is generated based on the selected one or more activation functions and the intermediate output, and one or more actions are taken based on the generated output.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Inventors: Mustafa KESKIN, Fatih Murat PORIKLI
  • Publication number: 20240310888
    Abstract: A method for recovering from a power failure includes detecting a power collapse at a first voltage regulator supplying a first subsystem. The method also includes coupling a supply voltage rail or a voltage supply node of the first subsystem to a second voltage source, in response to detecting the power collapse at the first voltage regulator. The method further includes receiving power, at the first subsystem, from the second voltage source in response to the coupling of the first subsystem to the second voltage source.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 19, 2024
    Inventor: Mustafa KESKIN
  • Publication number: 20240289594
    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for improved hidden Markov model (HMM)-based machine learning. A sequence of observations is accessed. A hidden Markov model (HMM) comprising a set of transition probabilities, a set of emission probabilities, a transition coefficient hyperparameter, and an emission coefficient hyperparameter is also accessed, and a first output inference from the HMM is generated based on the sequence of observations.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 29, 2024
    Inventors: Mustafa KESKIN, Fatih Murat PORIKLI
  • Publication number: 20240248202
    Abstract: Aspects presented herein may enable a wireless device to dynamically change the frequencies of its pilot tones based on the distance of one or more objects detected, thereby enabling the wireless device to utilize the advantages of both high frequency pilot tone and low frequency pilot tone. In one aspect, a wireless device transmits a first pilot tone at a first frequency. The wireless device detects whether there is an object within a specified distance of the wireless device based on a reflected signal of the first pilot tone. The wireless device transmits a second pilot tone at a second frequency based on at least one object being detected within the specified distance, where the second frequency is higher than the first frequency. The wireless device calculates a first distance of the at least one object with respect to the wireless device based the second pilot tone.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Inventors: Kee-Hyun PARK, Mustafa KESKIN, Sungrack YUN
  • Publication number: 20240214016
    Abstract: Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and other aspects of spur suppression in millimeter wave receivers. In one aspect a local oscillator (LO) source is coupled to a quadrature generation circuit having a first output for a first LO signal, and a second output for a second LO signal 90 degrees out of phase with the first LO signal. Each output is coupled to an LO driver, and outputs of the LO drivers a coupled at a first power connection to provide spur suppression associated with a phase difference between the first LO signal and the second LO signal. Similar connections are provided at outputs of first and second mixers for spur suppression.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Chirag Dipak PATEL, Gary Lee BROWN, JR., Rajagopalan RANGARAJAN, Mustafa KESKIN
  • Publication number: 20240106395
    Abstract: Aspects described herein include devices and methods for an envelope tracking power supply. In some aspects, the envelope tracking power supply includes an envelope signal input port, an output power port, an input interface circuit coupled to the envelope signal input port, sensing and conditioning circuitry, and amplifier circuitry coupled between the input interface circuit and the sensing and conditioning circuitry, the amplifier circuitry having one or more control inputs. The envelope tracking power supply additionally includes switcher circuitry coupled to the output of the sensing and conditioning circuitry, and the output power port, and the supply further includes output filter circuitry coupled to the output power port and machine learning circuitry configured to receive state tracking data for performance of a transmit power amplifier (PA) that receives power via the output power port.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Mustafa KESKIN, Paul Brian SHEEHY
  • Publication number: 20240106467
    Abstract: Aspects described herein include devices and methods for generating a supply voltage for a power amplifier. One aspect is an apparatus including a first amplifier and a second amplifier having a control input, where the control input of the second amplifier is configured to set a power state for the second amplifier. The apparatus has an input interface circuit coupled to the two amplifiers, sensing and conditioning circuitry coupled between the amplifier outputs and switcher circuitry, and output filter circuitry, where the output of the first amplifier is coupled to an output power port via the output filter circuitry, and where the output of the second amplifier is coupled to the output power port via the output filter circuitry.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Mustafa KESKIN, Paul Brian SHEEHY
  • Publication number: 20230297335
    Abstract: A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 21, 2023
    Inventors: Mustafa KESKIN, Francois Ibrahim ATALLAH
  • Publication number: 20230168728
    Abstract: Methods and apparatus for supplying power to a dynamic load, such as a neural network circuit. One example power supply circuit generally includes a voltage regulator circuit and a distribution circuit coupled to one or more outputs of the voltage regulator circuit. The distribution circuit is configured to output different amounts of current based on changes in the dynamic load. For certain aspects, the dynamic load includes a neural network circuit having a plurality of segments. In this case, the distribution circuit may be configured to output the different amounts of current based on which segment in the plurality of segments of the neural network circuit is active.
    Type: Application
    Filed: November 29, 2022
    Publication date: June 1, 2023
    Inventors: Mustafa KESKIN, Guoqing MIAO, Sameer WADHWA
  • Publication number: 20230098996
    Abstract: An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Yi-Hung Tseng, Marzio Pedrali-Noy, Charles James Persico, Mustafa Keskin
  • Publication number: 20230057454
    Abstract: Certain aspects of the present disclosure provide techniques for parameterized activation functions. Input data is processed with at least one layer of the neural network model comprising a parameterized activation function, and at least one trainable parameter of the parameterized activation function is updated based at least in part on output from the at least one layer of the neural network model. The at least one trainable parameter may adjust at least one of a range over which the parameterized activation function is nonlinear or a shape of the parameterized activation function, and/or may adjust a location of at least one pivot of the parameterized activation function.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Jamie Menjay LIN, Fatih Murat PORIKLI, Mustafa KESKIN
  • Patent number: 11342927
    Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 24, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Younghyun Lim, Yiwu Tang, Dongmin Park, Yunliang Zhu, Mustafa Keskin, Yue Chao
  • Patent number: 11334101
    Abstract: A method and an apparatus to provide bandgap calibration for multiple outputs are disclosed. In one implementation, a computing chip includes a bandgap current generator; a first adjustable current output coupled to the bandgap current generator; a second adjustable current output coupled to the bandgap current generator; a first switch selectively coupling the first adjustable current output to a calibration circuit and to a first analog-to-digital converter (ADC); and a second switch selectively coupling the second adjustable current output to a load on the computing chip and to the ADC.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 17, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Baptiste Grave, Mustafa Keskin
  • Publication number: 20210397937
    Abstract: A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 23, 2021
    Inventors: Mustafa KESKIN, Ankit SRIVASTAVA, Sameer WADHWA, Guoqing MIAO
  • Publication number: 20210191437
    Abstract: A method and an apparatus to provide bandgap calibration for multiple outputs are disclosed. In one implementation, a computing chip includes a bandgap current generator; a first adjustable current output coupled to the bandgap current generator; a second adjustable current output coupled to the bandgap current generator; a first switch selectively coupling the first adjustable current output to a calibration circuit and to a first analog-to-digital converter (ADC); and a second switch selectively coupling the second adjustable current output to a load on the computing chip and to the ADC.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Baptiste GRAVE, Mustafa KESKIN