Patents by Inventor Mysore Sathyanarayana Srinivas

Mysore Sathyanarayana Srinivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9086888
    Abstract: A method for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wen-Tzer T. Chen, Diane G. Flemming, William A. Maron, Mysore Sathyanarayana Srinivas, David Blair Whitworth
  • Patent number: 8930670
    Abstract: Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss in response to determining the page address miss in a page addressing buffer, and saving the mapping as an entry in an array. The computer implemented method creates a preserved array from the array in response to determining the dispatched partition to be an undispatched partition. The computer implemented method further analyzes of the preserved array for a compressed page in response to determining the undispatched partition is now redispatched, and decompresses the compressed page prior to the partition being redispatched.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Bret R. Olszewski, Mysore Sathyanarayana Srinivas
  • Patent number: 8832416
    Abstract: An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wen-Tzer Thomas Chen, Venkat Rajeev Indukuru, Alexander Erik Mericas, Mysore Sathyanarayana Srinivas
  • Patent number: 8806153
    Abstract: A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Herman Dietrich Dierks, Hong Lam Hua, Mysore Sathyanarayana Srinivas
  • Publication number: 20140156979
    Abstract: A method for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: Wen-Tzer T. Chen, Diane G. Flemming, William A. Maron, Mysore Sathyanarayana Srinivas, David Blair Whitworth
  • Patent number: 8745622
    Abstract: Standalone software performance optimizer systems for hybrid systems include a hybrid system having a plurality of processors, memory operably connected to the processors, an operating system including a dispatcher loaded into the memory, a multithreaded application read into the memory, and a static performance analysis program loaded into the memory; wherein the static performance analysis program instructs at least one processor to perform static performance analysis on each of the threads, the static performance analysis program instructs at least one processor to assign each thread to a CPU class based on the static performance analysis, and the static performance analysis program instructs at least one processor to store each thread's CPU class.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Greg R. Mewhinney, Diane Garza Flemming, David B. Whitworth, William A. Maron, Mysore Sathyanarayana Srinivas
  • Patent number: 8688960
    Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew Accapadi, Robert H. Bell, Jr., Hong Lam Hua, Ram Raghavan, Mysore Sathyanarayana Srinivas
  • Patent number: 8688961
    Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew Accapadi, Robert H. Bell, Jr., Hong Lam Hua, Ram Raghavan, Mysore Sathyanarayana Srinivas
  • Patent number: 8566539
    Abstract: A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, Ghadir Robert Gholami, Octavian Florin Herescu, William A Maron, Mysore Sathyanarayana Srinivas
  • Patent number: 8447955
    Abstract: A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dunshea, Satya Prakash Sharma, Mysore Sathyanarayana Srinivas
  • Patent number: 8438338
    Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
    Type: Grant
    Filed: August 15, 2010
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
  • Patent number: 8417889
    Abstract: An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
  • Patent number: 8392659
    Abstract: A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Diane Garza Flemming, William A. Maron, Mysore Sathyanarayana Srinivas
  • Patent number: 8291430
    Abstract: A mechanism for optimizing system performance using spare processing cores in a virtualized environment. When detecting a workload partition needs to run on a virtual processor in the virtualized system, a state of the virtual processor is changed to a wait state. A first node comprising memory that is local to the workload partition is determined. A determination is also made as to whether a non-spare processor core in the first node is available to run the workload partition. If no non-spare processor core is available, a free non-spare processor core in a second node is located, and the state of the free non-spare processor core in the second node is changed to an inactive state. The state of a spare processor core in the first node is changed to an active state, and the workload partition is dispatched to the spare processor core in the first node for execution.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Mysore Sathyanarayana Srinivas
  • Publication number: 20120260257
    Abstract: A computer program product for scheduling threads in a multiprocessor computer comprises computer program instructions configured to select a thread in a ready queue to be dispatched to a processor and determine whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, the computer program instructions are configured to select a processor, set a current processor priority register of the selected processor to least favored, and dispatch the thread from the ready queue to the selected processor.
    Type: Application
    Filed: June 20, 2012
    Publication date: October 11, 2012
    Applicant: International Business Machines Corporation
    Inventors: Jos Manuel Accapadi, Mathew Accapadi, Andrew Dunshea, Mark Elliott Hack, Agustin Mena, III, Mysore Sathyanarayana Srinivas
  • Patent number: 8275802
    Abstract: A method, computer program product, and a data processing system for maintaining objects in a lookup cache is provided. A primary list is populated with a first plurality of objects. The primary list is an unordered list of the first plurality of objects. A secondary list is populated with a second plurality of objects. The secondary list is an ordered list of the second plurality of objects. Periodically, at least one object of the first plurality of objects is demoted to the secondary list, and at least one object of the second plurality of objects is promoted to the primary list.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Greg R. Mewhinney, Mysore Sathyanarayana Srinivas
  • Publication number: 20120215982
    Abstract: A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.
    Type: Application
    Filed: February 22, 2011
    Publication date: August 23, 2012
    Applicant: International Business Machines Corporation
    Inventors: Robert H. Bell, JR., Herman Dietrich Dierks, Hong Lam Hua, Mysore Sathyanarayana Srinivas
  • Patent number: 8146087
    Abstract: A system and method for allowing jobs originating from different partitions to simultaneously utilize different hardware threads on a processor by concatenating partition identifiers with virtual page identifiers within a processor's translation lookaside buffer is presented. The device includes a translation lookaside buffer that translates concatenated virtual addresses to system-wide real addresses. The device generates concatenated virtual addresses using a partition identifier, which corresponds to a job's originating partition, and a virtual page identifier, which corresponds to the executing instruction, such as an instruction address or data address. In turn, each concatenated virtual address is different, which translates in the translation lookaside buffer to a unique system-wide real address. As such, jobs originating from different partitions are able to simultaneously execute on the device and, therefore, fully utilize each of the device's hardware threads.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Men-Chow Chiang, Sujatha Kashyap, Mysore Sathyanarayana Srinivas
  • Publication number: 20120042131
    Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
    Type: Application
    Filed: August 15, 2010
    Publication date: February 16, 2012
    Applicant: International Business Machines Corporation
    Inventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
  • Patent number: 8104036
    Abstract: In a multiprocessor system where each processor has the capacity to executing multiple hardware threads, a processor capacity monitor calculates a logical usage percentage of each of the available hardware threads. The processor capacity monitor calculates a physical usage percentage of each of the processors by each of the available threads. The processor capacity monitor calculate a percentage usage of a total capacity of the physical processors from the logical usage percentages and the physical usage percentages, such that the percentage usage reflects the actual use of the physical processors independent of which of the threads is used.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bret Ronald Olszewski, Luc Rene Smolders, Mysore Sathyanarayana Srinivas