Abstract: A semiconductor package including a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a third semiconductor chip disposed on the second semiconductor chip. A first pad is disposed on a top surface of the second semiconductor chip, and includes a first portion and a second portion protruding in a vertical direction from the first portion. A width of the first portion in a first horizontal direction is greater than a width of the second portion in the first horizontal direction. A second pad is disposed on a bottom surface of the third semiconductor chip facing the top surface of the second semiconductor chip, and a solder ball is disposed as surrounding a sidewall of the second portion of the first pad between the first pad and the second pad.

Abstract: A semiconductor package including a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a third semiconductor chip disposed on the second semiconductor chip. A first pad is disposed on a top surface of the second semiconductor chip, and includes a first portion and a second portion protruding in a vertical direction from the first portion. A width of the first portion in a first horizontal direction is greater than a width of the second portion in the first horizontal direction. A second pad is disposed on a bottom surface of the third semiconductor chip facing the top surface of the second semiconductor chip, and a solder ball is disposed as surrounding a sidewall of the second portion of the first pad between the first pad and the second pad.

Abstract: A semiconductor package including a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a third semiconductor chip disposed on the second semiconductor chip. A first pad is disposed on a top surface of the second semiconductor chip, and includes a first portion and a second portion protruding in a vertical direction from the first portion. A width of the first portion in a first horizontal direction is greater than a width of the second portion in the first horizontal direction. A second pad is disposed on a bottom surface of the third semiconductor chip facing the top surface of the second semiconductor chip, and a solder ball is disposed as surrounding a sidewall of the second portion of the first pad between the first pad and the second pad.

Abstract: In a method of debonding a carrier substrate from a device substrate, an ultraviolet (UV) light may be irradiated to an adhesive tape through the carrier substrate, which may be attached to a first surface of the device substrate having a connection post using the adhesive tape, to weaken an adhesive force of the adhesive tape. An outskirt portion of the carrier substrate may be masked to concentrate the UV light on the adhesive tape.

Abstract: In a method of debonding a carrier substrate from a device substrate, an ultraviolet (UV) light may be irradiated to an adhesive tape through the carrier substrate, which may be attached to a first surface of the device substrate having a connection post using the adhesive tape, to weaken an adhesive force of the adhesive tape. An outskirt portion of the carrier substrate may be masked to concentrate the UV light on the adhesive tape.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: A multi-chip package device can include a plurality of integrated circuit device chips stacked on one another inside a multi-chip package including the device. The device can include an electrically isolated multi-chip support structure that is directly connected to first and second electrically active integrated circuit structures via respective first and second adhesive layers located on opposing sides of the electrically isolated multi-chip support structure.

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract: A semiconductor package forming method includes mounting a backgrinding-underfill film which includes a laminated backgrinding film and a laminated underfill film on a semiconductor wafer so that the underfill film adheres to a front side of the semiconductor wafer; backgrinding a back side of the semiconductor wafer on which the backgrinding-underfill film has been mounted and removing the backgrinding film of the backgrinding-underfill film from the semiconductor wafer. The method further includes dicing the semiconductor wafer from which the backgrinding film has been removed, so that semiconductor chips are separated from the semiconductor wafer.

Abstract: A semiconductor package forming method includes mounting a backgrinding-underfill film which includes a laminated backgrinding film and a laminated underfill film on a semiconductor wafer so that the underfill film adheres to a front side of the semiconductor wafer; backgrinding a back side of the semiconductor wafer on which the backgrinding-underfill film has been mounted and removing the backgrinding film of the backgrinding-underfill film from the semiconductor wafer. The method further includes dicing the semiconductor wafer from which the backgrinding film has been removed, so that semiconductor chips are separated from the semiconductor wafer.

Abstract: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

Abstract: Provided are a thin semiconductor chip pickup apparatus and method for detaching a die bonding film from a semiconductor chip using the apparatus. The apparatus may include a stage for supporting a die-bonding film to which a semiconductor chip is attached, a plurality of suction members arranged on the center of the stage for extracting the die-bonding film by a vacuum, where the suction members detach the die-bonding film away from the semiconductor chip to form a vacuum region, and a plurality of vacuum suction ports respectively interposed between adjacent suction members to allow the suction members to detach the die-bonding film by the vacuum.

Abstract: A semiconductor package has ball lands each configured to have a composite structure of SMD type and NSMD type. One peripheral portion of the ball land is covered with a mask layer, thus forming the SMD type, whereas the other peripheral portion is exposed through an opening area of the mask layer, thus forming the NSMD type. In one embodiment, the first peripheral portion is disposed to face a central point of a ball-mounting surface of a substrate, and the second peripheral portion is disposed to face the opposite direction to the central point. The composite structure of the ball lands provides more stable and enhanced connections between connection balls, such as solder balls, and the ball-mounting surface.

Abstract: A semiconductor package has ball lands each configured to have a composite structure of SMD type and NSMD type. One peripheral portion of the ball land is covered with a mask layer, thus forming the SMD type, whereas the other peripheral portion is exposed through an opening area of the mask layer, thus forming the NSMD type. In one embodiment, the first peripheral portion is disposed to face a central point of a ball-mounting surface of a substrate, and the second peripheral portion is disposed to face the opposite direction to the central point. The composite structure of the ball lands provides more stable and enhanced connections between connection balls, such as solder balls, and the ball-mounting surface.

Abstract: A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Abstract: A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N-1) chip selection pads, an insulation layer, (N-1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.