Patents by Inventor Nadav Bonen

Nadav Bonen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11687681
    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: June 27, 2023
    Assignee: INTEL CORPORATION
    Inventors: Shay Gueron, Siddhartha Chhabra, Nadav Bonen
  • Patent number: 11520498
    Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Sridhar Muthrasanallur, Srinivas Pandruvada, Vishwanath Somayaji, Prashant Kodali
  • Publication number: 20220262427
    Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 18, 2022
    Applicant: Intel Corporation
    Inventors: Nivedha Krishnakumar, Virendra Vikramsinh Adsure, Jaya Jeyaseelan, Nadav Bonen, Barnes Cooper, Toby Opferman, Vijay Bahirji, Chia-Hung Kuo
  • Publication number: 20210405892
    Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.
    Type: Application
    Filed: December 9, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Nadav Bonen, Sridhar Muthrasanallur, Srinivas Pandruvada, Vishwanath Somayaji, Prashant Kodali
  • Publication number: 20210103682
    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.
    Type: Application
    Filed: September 14, 2020
    Publication date: April 8, 2021
    Inventors: Shay Gueron, Siddhartha Chhabra, Nadav Bonen
  • Patent number: 10877693
    Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Julius Mandelblat, Nir Sucher
  • Patent number: 10802567
    Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
  • Patent number: 10776525
    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Siddhartha Chhabra, Nadav Bonen
  • Patent number: 10680613
    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Alexey Kostinsky, Nadav Bonen
  • Patent number: 10558570
    Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Zvika Greenfield, Randy Osborne
  • Publication number: 20190102577
    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Shay Gueron, Siddhartha Chhabra, Nadav Bonen
  • Publication number: 20190042157
    Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Nadav Bonen, Julius Mandelblat, Nir Sucher
  • Publication number: 20190036531
    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Kuljit S. BAINS, Alexey KOSTINSKY, Nadav BONEN
  • Patent number: 10141935
    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S Bains, Alexey Kostinsky, Nadav Bonen
  • Patent number: 10109340
    Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, John B. Halbert, Nadav Bonen, Tomer Levy
  • Patent number: 10055346
    Abstract: Apparatus, systems, and methods to implement polarity based data transfer function for volatile memory power reduction are described. The transfer function take into account certain data values, all zeroes in particular, that are common and transforms them to predetermined values that consume less power and are less common. Similarly, these predetermined values are transformed to the common values.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventor: Nadav Bonen
  • Publication number: 20180129266
    Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 10, 2018
    Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
  • Publication number: 20180129265
    Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 10, 2018
    Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
  • Patent number: 9948299
    Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Nadav Bonen, Christopher E. Cox, Alexey Kostinsky
  • Publication number: 20180067852
    Abstract: Apparatus, systems, and methods to implement polarity based data transfer function for volatile memory power reduction are described. The transfer function take into account certain data values, all zeroes in particular, that are common and transforms them to predetermined values that consume less power and are less common. Similarly, these predetermined values are transformed to the common values.
    Type: Application
    Filed: August 21, 2017
    Publication date: March 8, 2018
    Applicant: Intel Corporation
    Inventor: Nadav Bonen