Patents by Inventor Naftali Lustig
Naftali Lustig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11011415Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: GrantFiled: April 24, 2020Date of Patent: May 18, 2021Assignee: International Business Machines CorporationInventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Patent number: 10796949Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: GrantFiled: October 19, 2018Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Publication number: 20200258770Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: ApplicationFiled: April 24, 2020Publication date: August 13, 2020Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Publication number: 20200126842Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Patent number: 9425144Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.Type: GrantFiled: December 23, 2014Date of Patent: August 23, 2016Assignee: GlobalFoundries, Inc.Inventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali Lustig, Andrew H. Simon, Junjing Bao
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Patent number: 9105637Abstract: A method including a first interconnect level including a first electrode embedded in a first dielectric layer, a top surface of the first electrode is substantially flush with a top surface of the first dielectric layer, a second interconnect level including a via embedded in a second dielectric layer above the first dielectric layer, a third dielectric layer in direct contact with and separating the first dielectric layer and the second dielectric layer, an entire top surface of the first electrode is in direct physical contact with a bottom surface of the third dielectric layer, and an interface between the first dielectric layer and the third dielectric layer extending from the top surface of the first electrode to the via, the interface including a length less than a minimum width of the via, a bottom surface of the via is in direct physical contact with the first dielectric layer.Type: GrantFiled: May 18, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, Naftali Lustig, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20150137312Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.Type: ApplicationFiled: December 23, 2014Publication date: May 21, 2015Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali Lustig, Andrew H. Simon, Junjing Bao
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Publication number: 20130307115Abstract: A method and structure of a non-intrinsic anti-fuse structure. The anti-fuse structure has a first electrode, a second electrode, a first dielectric, and second dielectric. The first and second dielectrics have an interface which couples electrodes. The length along the interface which couples the electrodes is called the predetermined length. When the anti-fuse is programmed a conductive link forms along the interface to connect the first and second electrodes. The anti-fuse structure can be single-level or dual-level. The predetermined length can be less than spacing between adjacent electrodes when a dual-level structure is used. The anti-fuse structures have the advantage that they can be programmed at lower voltages than intrinsic structures and no extra steps are needed to integrate the anti-fuses with active structures.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: International Business Machines CorporationInventors: Ronald G. Filippi, Naftali Lustig, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 8129269Abstract: In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.Type: GrantFiled: September 20, 2010Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Junjing Bao, Tien-Jen J. Cheng, Naftali Lustig
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Publication number: 20050064658Abstract: MIM capacitors and thin film resistors are fabricated with at least one less lithographic step than the prior art methods. The process step reduction is realized by using semi-transparent metallic electrodes, fabricated with a two-mask process, which provides for direct alignment, and eliminates the need for alignment trenches in an additional layer.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn Biery, Zheng Chen, Timothy Dalton, Naftali Lustig
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Patent number: 6632377Abstract: Copper or a copper alloy is removed by chemical-mechanical planarization (CMP) in a slurry of an oxidizer, an oxidation inhibitor, and an additive that appreciably regulates copper complexing with the oxidation inhibitor.Type: GrantFiled: September 30, 1999Date of Patent: October 14, 2003Assignee: International Business Machines CorporationInventors: Vlasta Brusic, Daniel C. Edelstein, Paul M. Feeney, William Guthrie, Mark Jaso, Frank B. Kaufman, Naftali Lustig, Peter Roper, Kenneth Rodbell, David B. Thompson