Patents by Inventor Nagalinga Swamy Basayya Aremallapur
Nagalinga Swamy Basayya Aremallapur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11695602Abstract: A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.Type: GrantFiled: November 30, 2021Date of Patent: July 4, 2023Assignee: Texas Instruments IncorporatedInventors: Jaiganesh Balakrishnan, Nagalinga Swamy Basayya Aremallapur, Aswath Vs
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Publication number: 20230033830Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Sthanunathan RAMAKRISHNAN, Nithin GOPINATH, Sai Aditya NURANI, Joseph Palackal MATHEW, Nagalinga Swamy Basayya AREMALLAPUR
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Patent number: 11569827Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.Type: GrantFiled: July 30, 2021Date of Patent: January 31, 2023Assignee: Texas Instruments IncorporatedInventors: Sthanunathan Ramakrishnan, Nithin Gopinath, Sai Aditya Nurani, Joseph Palackal Mathew, Nagalinga Swamy Basayya Aremallapur
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Patent number: 11469928Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.Type: GrantFiled: June 30, 2021Date of Patent: October 11, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ani Xavier, Jagannathan Venkataraman, Nagalinga Swamy Basayya Aremallapur, Aviral Singhal, Arun Mohan, Rakesh Chikkanayakanahalli Manjunath, Aravind Ganesan, Harshavardhan Adepu
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Patent number: 11418148Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.Type: GrantFiled: November 20, 2020Date of Patent: August 16, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nagalinga Swamy Basayya Aremallapur, Sriram Murali, Jawaharlal Tangudu
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Publication number: 20220182266Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.Type: ApplicationFiled: June 30, 2021Publication date: June 9, 2022Inventors: Ani Xavier, Jagannathan Venkataraman, Nagalinga Swamy Basayya Aremallapur, Aviral Singhal, Arun Mohan, Rakesh Chikkanayakanahalli Manjunath, Aravind Ganesan, Harshavardhan Adepu
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Publication number: 20220182098Abstract: A technique for reinitializing a coupled circuit, the technique including receiving a common configuration value associated with states of a coupled circuit, tracking states associated with the coupled circuit while the coupled circuit is in a low power state based on the common configuration value, receiving the tracked state associated with the coupled circuit, receiving a scaling value associated with the coupled circuit, determining a current state of the coupled circuit based on the tracked state and the scaling value, and transmitting an indication of the current state to the coupled circuit when the coupled circuit has exited the low power state.Type: ApplicationFiled: December 7, 2021Publication date: June 9, 2022Inventors: Sundarrajan RANGACHARI, Nagalinga Swamy Basayya AREMALLAPUR, Kalyan GUDIPATI, Divyeshkumar Mahendrabhai PATEL, Venkateshwara Reddy POTHAPU, Aravind VIJAYAKUMAR, Sarma Sundareswara GUNTURI, Jaiganesh BALAKRISHNAN
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Publication number: 20220173947Abstract: A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.Type: ApplicationFiled: November 30, 2021Publication date: June 2, 2022Inventors: Jaiganesh BALAKRISHNAN, Nagalinga Swamy Basayya AREMALLAPUR, Aswath VS
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Publication number: 20220066975Abstract: A circuit includes: a parallel data interface; and transition control circuitry coupled to the parallel data interface. The transition control circuitry is configured to: receive an input bit stream sample; determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria; and generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample.Type: ApplicationFiled: June 30, 2021Publication date: March 3, 2022Inventors: Aravind GANESAN, Nagalinga Swamy Basayya AREMALLAPUR, Jaiganesh BALAKRISHNAN, Robert Clair KELLER
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Publication number: 20210075368Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.Type: ApplicationFiled: November 20, 2020Publication date: March 11, 2021Inventors: Nagalinga Swamy Basayya AREMALLAPUR, Sriram MURALI, Jawaharlal TANGUDU
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Patent number: 10879845Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.Type: GrantFiled: May 6, 2019Date of Patent: December 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nagalinga Swamy Basayya Aremallapur, Sriram Murali, Jawaharlal Tangudu
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Patent number: 10840919Abstract: A clock data recovery circuit includes a phase detector (PD) having a data input, a second input, and an output. The circuit also includes a filter, first and second charge pumps, a voltage-controlled oscillator (VCO), and a frequency detector (FD). The first charge pump couples between the output of the PD and the filter. The VCO has first and second inputs and an output. The first input of the VCO couples to the filter, and the VCO output couple to the second input of the PD. The FD has a data input, a second input, and first and second outputs. The FD second output couples to the second input of the VCO. The FD data input couples to the data input of the phase detector, and the FD second input couples to the output of the VCO. The second charge pump couples between the FD first output and the filter.Type: GrantFiled: April 29, 2020Date of Patent: November 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shyam Subramanian, Nagalinga Swamy Basayya Aremallapur, Jagannathan Venkataraman, Aravind Ganesan
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Publication number: 20200212844Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.Type: ApplicationFiled: May 6, 2019Publication date: July 2, 2020Inventors: Nagalinga Swamy Basayya AREMALLAPUR, Sriram MURALI, Jawaharlal TANGUDU
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Patent number: 10693444Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.Type: GrantFiled: April 29, 2019Date of Patent: June 23, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nagalinga Swamy Basayya Aremallapur, Eeshan Miglani, Visvesvaraya Pentakota, Praxal Sunilkumar Shah
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Publication number: 20200177170Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.Type: ApplicationFiled: February 21, 2019Publication date: June 4, 2020Inventors: Gautam Sanjay KALE, Sundarrajan RANGACHARI, Nagalinga Swamy Basayya AREMALLAPUR
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Publication number: 20200177168Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.Type: ApplicationFiled: April 29, 2019Publication date: June 4, 2020Inventors: Nagalinga Swamy Basayya AREMALLAPUR, Eeshan MIGLANI, Visvesvaraya PENTAKOTA, Praxal Sunilkumar SHAH
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Patent number: 10651836Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.Type: GrantFiled: February 21, 2019Date of Patent: May 12, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gautam Sanjay Kale, Sundarrajan Rangachari, Nagalinga Swamy Basayya Aremallapur
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Publication number: 20190273601Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.Type: ApplicationFiled: May 21, 2019Publication date: September 5, 2019Inventors: Jaiganesh BALAKRISHNAN, Shagun DUSAD, Visvesvaraya PENTAKOTA, Srinivas Kumar Reddy NARU, Sarma Sundareswara GUNTURI, Nagalinga Swamy Basayya AREMALLAPUR
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Patent number: 10341082Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.Type: GrantFiled: February 27, 2018Date of Patent: July 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaiganesh Balakrishnan, Shagun Dusad, Visvesvaraya Pentakota, Srinivas Kumar Reddy Naru, Sarma Sundareswara Gunturi, Nagalinga Swamy Basayya Aremallapur
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Patent number: 10205455Abstract: The disclosure provides a universal oscillator. The oscillator includes an amplifier array. The amplifier array includes one or more amplifiers. A control logic unit is coupled to the amplifier array and activates the one or more amplifiers. A self-clock generating circuit is coupled to the control logic unit and generates a fixed clock. A counter receives the fixed clock from the self-clock generating circuit and provides a controlled clock to the control logic unit.Type: GrantFiled: August 23, 2016Date of Patent: February 12, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Nagalinga Swamy Basayya Aremallapur