Abstract: A power converting apparatus for system interconnecting includes a self-commutated converter, DC supply or direct capacitor connected to a DC terminal of the self-commutated converter, a series reactor or transformer, connected between an AC terminal of the self-commutated converter and an AC power system. The self-commutated converter includes a plurality of semiconductor valves connected in bridge between P bus and N bus of the DC supply. The semiconductor valves respectively includes a plurality of series-connected nonlatch devices, a series snubber circuit connected in series to the plurality of series-connected nonlatch devices, and a voltage balancing resistor and a plurality parallel snubber circuits respectively which includes a clipper circuit and a series circuit. The series circuit comprises a snubber capacitor and snubber resistor.

Abstract: The power conversion system of this invention comprises line-commutated power converting means in which a line-commutated power conversion circuit that performs line-commutated commutation and a coupling diode are coupled to form a DC circuit and for converting DC power into AC power or AC power into DC power. Further, the system comprises self-commutated power converting means, in which a self-commutated power conversion circuit is coupled to the coupling diode in order to form a DC circuit and for reducing reactive power, or the reactive power and harmonics generated by the line-commutated converting means. Accordingly, their respective strengths can be made use of and their mutual weaknesses can complement each other.

Abstract: A conversion apparatus including a plurality of high-speed switching devices, each being operable in latch type operation and non-latch type operation and a power source for supplying a first current to the high-speed switching devices, thereby forming a current path of the high-speed switching devices. The high-speed switching device is turned off after changeover from the latch type operation to the non-latch type operation. The conversion apparatus further includes a current regulation circuit provided in the current path for regulating a second current flowing through the current regulation circuit after the second current has reached a prescribed value. In case of overcurrent malfunction, the high-speed switching device is changed from the latch type operation to the non-latch type operation, and then is caused to be turned off while the current regulation circuit regulates the second current.

Abstract: A power converter device including a plurality of self-commutated voltage type converter each connected to a common d.c. circuit, a plurality of transformers each having d.c. windings and a.c. windings, each of the d.c. windings being connected to an a.c. output terminal of a respective one of the converters and each of the a.c. windings being connected in series, an a.c. switch through which the serially connected a.c. windings of the transformers are adapted to be connected to a utility power system, and a d.c. overvoltage suppression device, installed in the common d.c. circuit, wherein the transformers are connected to the utility power system by synchronous making, and the d.c. overvoltage suppression device is connected to the common d.c. circuit when the converters are stopped temporarily.

Abstract: A power converter device including a plurality of self-commutated voltage type converters each connected to a common dc circuit, a plurality of transformers each having dc windings and ac windings, each of the dc windings being connected to an ac output terminal of a respective one of the converters and each of the ac windings connected in series, an ac switch through which the serially connected ac windings of the transformers are connected to utility power systems, a capacitor provided in the common dc circuit, a dc overvoltage suppression means installed in the common dc circuit, and a current limiting device, wherein the capacitor in the common dc circuit is charged through the current limiting device means before starting the self-commutated voltage type converters, and the dc overvoltage suppression means is then connected to the common dc circuit and removed after the self-commutated voltage type converters are started.

Abstract: In a system interconnecting inverter apparatus, an inverter for controlling power of an AC power system is coupled, via a coupling reactor, to the AC power system having a system voltage. A system phase signal indicating the phase of the system voltage is detected by a system phase detection circuit in real time. Another phase signal indicating the phase of the system voltage is detected by a comparison phase detection circuit with a predetermined delay time, and the detection result is temporarily stored in the circuit as a comparison phase signal. The system phase signal and the comparison phase signal are phase-compared by a stop circuit. When a phase difference between the system phase signal and the comparison phase signal exceeds a predetermined value, the stop circuit stops the operation of the inverter.

Abstract: A power converter including a plurality of serially connected self-turn-off semiconductor elements, including a first control circuit for producing a plurality of control signals, and a plurality of second control circuits is connected to receive respective of the control signals to supply a non-conduction control signal to a respective of the self-turn-off semiconductor elements to turn off the respective semiconductor element. The power converter further includes a plurality of failure detectors and blocking circuits. Each of the failure detectors is connected to a respective of the self-turn-off semiconductor elements for detecting a fault thereof to produce a fault detection signal when the respective self-turn-off semiconductor elements has failed. Each of the blocking circuits is connected to the respective failure detector and to the first control circuit for blocking either the respective control signal or the respective non-conduction control signal based on the respective fault detection signal.

Abstract: A power converter apparatus for use in supplying power from a DC power source to a load, including a chopper connected to the DC power source; an inverter connected to a DC output of the chopper for supplying converted AC power to the load; an error amplifier for detecting an output voltage of the power converter apparatus and controlling the output voltage so as to maintain the output voltage equal to a predetermined reference value; and a voltage control circuit for generating a gate signal for the chopper, including an oscillator circuit for producing a variable frequency signal having a frequency varied in accordance with an output signal of the error amplifier, and a phase shifter for producing the gate signal with a pulse width varied in synchronism with the output signal of the oscillator circuit and for applying the pulse width varied gate signal to the chopper. In this way the chopper frequency is decreased to improve the operating efficiency during light-load operation.

Abstract: A gate-turn-off thyristor failure detecting circuit includes a detector which detects an off-gate signal for a gate-turn-off thyristor and a current level detector which compares the signal with a predetermined value and produces an output signal indicative of the failure of the gate-turn-off thyristor.

Abstract: A gate circuit for turning off a gate turn-off thyristor providing a signal of rapid voltage rise and high peak value followed by successive signals of low peak value. The circuit uses a pulse transformer, whose primary winding is divided at least into three windings, which is associated with three winding capacitors which are respectively connected with the connection points of the divided primary windings.

Abstract: A multiple inverter has an input shut-off circuit receiving a DC energy input and providing two DC outputs; two unit inverters coupled to the input shut-off circuit, each including switching elements, for respectively converting the DC outputs into two AC outputs; and a control circuit coupled to the unit inverters for detecting an accidental overcurrent due to a shoot-through of the switching elements, and turning off the unit inverters. The input shut-off circuit includes circuit elements for interrupting a current path of the DC energy input when the control circuit detects the accidental or faulty overcurrent.

Abstract: A gate circuit of a gate turn-off thyristor has first and second circuit means. The first circuit means consists of a diode, a pulse transformer with a voltage dividing point in the primary section, and a switching element. The transformer provides a pulse current of a large rising rate between the cathode and gate of the thyristor when the switching element is closed and also provides a pulse current of a smaller falling rate between the cathode and gate when the switching element is open. The second circuit means consists of at least a single capacitor, which is connected between the voltage dividing point of the transformer and a d.c.

Abstract: In controlled apparatus in which the output pulses of a common reference oscillator are the reference signals of a plurality of inverters, a synchronizing signal generated once in each cycle is added to the output pulses of the common reference oscillator. A respective control apparatus provided for each inverter detects the synchronizing signal from these output pulses to which the synchronizing signal has been added, and by this means phase matching of the outputs of the inverters is effected.

Abstract: There are arranged an oscillator for generating a first pulse signal on which the AC output frequency of the inverter is based, a delay circuit for generating a second pulse signal delayed for a predetermined period of time from the first pulse signal, and a ring counter for generating responsive to the second pulse signal a phase reference signal corresponding in phase to the AC output of the inverter. An ON pulse is generated responsive to the second pulse and the phase reference signal and an OFF pulse responsive to the first pulse and the phase reference signal. A negative bias signal is generated following the OFF pulse. At the time of operation stop the negative bias signal following the ON and OFF pulses is applied to GTO thyristors simultaneously.

Abstract: A snubber circuit is connected between the anode and cathode of a gate turn-off (GTO) thyristor. To the GTO thyristor a saturable reactor is connected in series. A gate off signal is supplied to the gate of the GTO thyristor and to the saturable reactor as backward current to reset the saturable reactor.

Abstract: A DC power source is provided with a rectifier circuit connected to an AC power source and a smoothing circuit, which is comprised of a DC reactor and a parallel capacitor, connected to the output terminal of the rectifier. A load is connected to the parallel capacitor. A diode is connected in a closed circuit including the parallel capacitor and the load, with such a polarity as to check discharging current discharged from the parallel capacitor. The diode forms the closed circuit, together with an auxiliary power source for applying through a reactor to the diode a voltage to make the diode conductive in forward direction. In short-circuiting accident of the load, a conducting circuit established between the auxiliary power source and the diode is shut off to block an excessive current flowing through the diode into a short-circuiting path between the parallel capacitor and the load.

Abstract: A first circuit means, which serves to cause reverse flow of a first pulse current of a large rate of rising and a narrow pulse width from cathode to gate of a gate turn-off thyristor in synchronism with the instant when turning off this thyristor, and a second circuit means, which serves to caus reverse flow of a second pulse current of a smaller rate of rising and a wider pulse width than the aforesaid first pulse current in superimposition thereupon from cathode to gate in synchronism with the turn-off instant, are provided.

Abstract: In controlled apparatus in which the output pulses of a common reference oscillator are the reference signals of a plurality of inverters, a synchronizing signal generated once in each cycle is added to the output pulses of the common reference oscillator. A respective control apparatus provided for each inverter detects the synchronizing signal from these output pulses to which the synchronizing signal has been added, and by this means phase matching of the outputs of the inverters is effected.