Patents by Inventor Nai-Wei LIU

Nai-Wei LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10429612
    Abstract: The invention discloses a three-piece optical lens for capturing image and a three-piece optical module for capturing image. In order from an object side to an image side, the optical lens along the optical axis comprises a first lens with positive refractive power; a second lens with refractive power; and a third lens with refractive power; and at least one of the image-side surface and object-side surface of each of the three lens elements are aspheric. The optical lens can increase aperture value and improve the imaging quality for use in compact cameras.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 1, 2019
    Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chien-Hsun Lai, Nai-Yuan Tang, Yao-Wei Liu, Yeong-Ming Chang
  • Patent number: 10429618
    Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens. At least one lens among the first to the sixth lenses has positive refractive force. The seventh lens has negative refractive force, wherein both surfaces thereof can be aspheric, and at least one surface thereof has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the seventh lenses. The optical image capturing system can increase aperture value and improve the imaging quality for use in compact cameras.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: October 1, 2019
    Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Nai-Yuan Tang, Yao-Wei Liu
  • Patent number: 10429617
    Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens. At least one lens among the first to the sixth lenses has positive refractive force. The seventh lens can have negative refractive force, and both surfaces thereof are aspheric. At least a surface of the seventh lens has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the seventh lenses. The optical image capturing system can increase aperture value and improve the imaging quality for use in compact cameras.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 1, 2019
    Assignee: Ability Opto-Electronics Technology Co., Ltd.
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Nai-Yuan Tang, Yao-Wei Liu
  • Publication number: 20190252351
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 15, 2019
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Ching-Wen Hsiao, Wei-Che Huang
  • Patent number: 10366960
    Abstract: An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
  • Patent number: 10295785
    Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens. At least one lens among the first to the sixth lenses has positive refractive force. The seventh lens can have negative refractive force, wherein both surfaces thereof are aspheric, and at least one surface thereof has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the seventh lenses. The optical image capturing system can increase aperture value and improve the imaging quality for use in compact cameras.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 21, 2019
    Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO. LTD.
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Nai-Yuan Tang, Yao-Wei Liu
  • Publication number: 20190131233
    Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
  • Patent number: 10217723
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 26, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
  • Publication number: 20190043771
    Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
    Type: Application
    Filed: June 7, 2018
    Publication date: February 7, 2019
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU
  • Patent number: 10199318
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
  • Publication number: 20180323127
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 8, 2018
    Applicant: MediaTek Inc.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Patent number: 10083913
    Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
  • Publication number: 20180269164
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.
    Type: Application
    Filed: February 27, 2018
    Publication date: September 20, 2018
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
  • Publication number: 20180269124
    Abstract: A semiconductor device includes a die having a pad, a passivation disposed aver the die and a portion of the pad, a polymer disposed over the passivation, a molding surrounding the die and the polymer, and an interface between the polymer and the molding. The interface and the passivation define an angle less than or greater than approximately 90°.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: NAI-WEI LIU, JUI-PIN HUNG, JING-CHENG LIN
  • Publication number: 20180233441
    Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
  • Patent number: 9978657
    Abstract: A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 9953907
    Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
  • Publication number: 20180102343
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Application
    Filed: July 10, 2017
    Publication date: April 12, 2018
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
  • Patent number: 9941260
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: April 10, 2018
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Chi-Chin Lien, Nai-Wei Liu, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Publication number: 20180033747
    Abstract: An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang