Abstract: A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.

Abstract: A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.

Abstract: A new method and apparatus to verify the performance of a built-in self-test circuit for testing embedded memory in an integrated circuit device is achieved. A set of faults is introduced into an embedded memory behavior model. The embedded memory behavior model comprises a high-level language model. Each member of the set of faults comprises a finite state machine state, a memory address, and a memory data fault. The built-in self-test circuit and the embedded memory behavior model are then simulated. The built-in self-test circuit generates input data and address patterns for the embedded memory behavior model. The embedded memory behavior model outputs memory address and data in response to the input data and address patterns. The input address and data and the memory address and data are compared in the built-in self-test circuit and a fault output is generated if not matching. The fault output and the set of faults are compared to verify the performance of the built-in self-test circuit.

Abstract: A power supply layout for an integrated circuit has a plurality of power pads, a plurality of ground pads, a plurality of first-type conductive wires directly connected to the power pad, a plurality of second-type conductive wires directly connected to the ground pad, and a core circuit electrically connected to the first-type and the second-type conductive wires for acquiring the operational power. The integrated circuit is made of a plurality of metal layers, wherein the first-type conductive wire and the second-type conductive wire are positioned at different metal layers. The power pad is positioned at the same metal layer as the first-type conductive wire, while the ground pad is positioned at the same metal layer as the second-type conductive wire.

Abstract: A method for modeling a memory with delay back annotation in accordance with the VITAL application specific integrated circuit modeling specification begins with modeling the memory with a timing generic and a port declaration. The wire delay of the memory is then modeled, followed by modeling a timing check for the memory. The wire delay of the model of the memory is then created. A description of the functional operation of the memory is then generated. The path delay for the address, control, and data bus signals to the memory is formed by overloading the VITAL path delay procedures. The VITAL timing check procedures are overloaded to determine timing constraint violations of the timing bus signals of the memory. The VITAL wire delay procedures are overloaded to determine interconnection delay bus signals of the memory.

Abstract: A BIST controller and a separate measurement circuit are used to determine the maximum time period for accessing data stored in an embedded integrated circuit memory. The BIST controller includes a finite state controller for controlling the state of said BIST, a pattern generator for generating a patterned stimulus to be applied to the memory, and a comparator for comparing the response of said memory to said stimulus, to a reference response. The measurement circuit includes a pair of logic circuits for respectively operating on “1's” and “0's” data read from the memory, and a plurality of time delay elements that introduce time delays in the data prior to delivery to the logic circuits.

Abstract: A BIST controller and a separate measurement circuit are used to determine the maximum time period for accessing data stored in an embedded integrated circuit memory. The BIST controller includes a finite state controller for controlling the state of said BIST, a pattern generator for generating a patterned stimulus to be applied to the memory, and a comparator for comparing the response of said memory to said stimulus, to a reference response. The measurement circuit includes a pair of logic circuits for respectively operating on “1's” and “0's” data read from the memory, and a plurality of time delay elements that introduce time delays in the data prior to delivery to the logic circuits.