Patents by Inventor Naim Ben-Hamida
Naim Ben-Hamida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120935Abstract: A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.Type: ApplicationFiled: October 7, 2022Publication date: April 11, 2024Applicant: Ciena CorporationInventors: Mouna Safi-Harab, Soheyl Ziabakhsh Shalmani, Sadok Aouini, Naim Ben-Hamida
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Publication number: 20240080178Abstract: Aspects of the subject disclosure may include, for example, a device including a phase rotator configured to receive a read clock, a flip flop configured to obtain an incoming data stream, and a controller. The controller may be configured to control the phase rotator to perform phase rotation of the read clock based on information-carrying level transitions in the incoming data stream, cause a gapped read clock and an inversion of the gapped read clock to be derived in accordance with the phase rotation, where the gapped read clock being derived via gapping operations associated with the read clock, and output clock selection signals that enable the flip flop to selectively sample the incoming data stream using the gapped read clock and the inversion, thereby facilitating a data handoff between asynchronous clock domains. Other embodiments are disclosed.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Applicant: CIENA CORPORATIONInventors: Andrew McCarthy, Sadok Aouini, Manoj Verghese, Naim Ben-Hamida
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Publication number: 20240030932Abstract: Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Applicant: Ciena CorporationInventors: Tingjun Wen, Sadok Aouini, Naim Ben-Hamida, Matthew Mikkelsen, Soheyl Ziabakhsh Shalmani, Mohammad Honarparvar
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Publication number: 20230412187Abstract: Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.Type: ApplicationFiled: October 29, 2021Publication date: December 21, 2023Inventors: Mohammad Honarparvar, Sadok Aouini, Jerry Yee-Tung Lam, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida
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Patent number: 11818242Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.Type: GrantFiled: September 10, 2020Date of Patent: November 14, 2023Inventors: Ahmad Abdo, Shahab Oveis Gharan, Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Lukas Jakober, Yalmez M. A. Yazaw
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Patent number: 11804847Abstract: A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.Type: GrantFiled: November 30, 2018Date of Patent: October 31, 2023Assignee: Ciena CorporationInventors: Sadok Aouini, Matthew Mikkelsen, Naim Ben-Hamida, Mahdi Parvizi, Tingjun Wen, Calvin Plett
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Patent number: 11770126Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.Type: GrantFiled: September 15, 2020Date of Patent: September 26, 2023Assignee: Ciena CorporationInventors: Mohammad Honarparvar, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida, Sadok Aouini
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Patent number: 11750287Abstract: An optical Digital Signal Processor (DSP) circuit includes a digital core configured to implement digital signal processing functionality and configured to operate at a plurality of baud rates including a full baud rate and a half-baud rate; and an analog interface including a Digital-to-Analog Converter (DAC) section and an Analog-to-Digital Converter (ADC) section, wherein the analog interface is connected to the digital core and is configured to operate at the full baud rate when the digital core is configured to operate at any of the plurality of baud rates.Type: GrantFiled: May 25, 2021Date of Patent: September 5, 2023Assignee: Ciena CorporationInventors: Sadok Aouini, Robert G. Gibbins, Yalmez Yazaw, Harvey Mah, Naim Ben-Hamida
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Publication number: 20230208428Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.Type: ApplicationFiled: September 15, 2020Publication date: June 29, 2023Inventors: Mohammad Honarparvar, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida, Sadok Aouini
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Patent number: 11561570Abstract: Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.Type: GrantFiled: December 1, 2020Date of Patent: January 24, 2023Assignee: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson
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Publication number: 20230006680Abstract: Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A card include first transmit (Tx) component configured to connect to a second receive (Rx) component in a second card; a first Rx component configured to connect to a second Tx component in the second card; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to compensate for differences between i) the first Tx component and the second Rx component, and ii) the first Rx component and the second Tx component.Type: ApplicationFiled: September 14, 2022Publication date: January 5, 2023Inventors: Jerry Yee-Tung Lam, Sadok Aouini, Naim Ben-Hamida
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Patent number: 11538511Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.Type: GrantFiled: February 11, 2021Date of Patent: December 27, 2022Assignee: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski
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Publication number: 20220385365Abstract: An optical Digital Signal Processor (DSP) circuit includes a digital core configured to implement digital signal processing functionality and configured to operate at a plurality of baud rates including a full baud rate and a half-baud rate; and an analog interface including a Digital-to-Analog Converter (DAC) section and an Analog-to-Digital Converter (ADC) section, wherein the analog interface is connected to the digital core and is configured to operate at the full baud rate when the digital core is configured to operate at any of the plurality of baud rates.Type: ApplicationFiled: May 25, 2021Publication date: December 1, 2022Inventors: Sadok Aouini, Robert G. Gibbins, Yalmez Yazaw, Harvey Mah, Naim Ben-Hamida
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Patent number: 11502695Abstract: Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.Type: GrantFiled: March 29, 2021Date of Patent: November 15, 2022Assignee: Ciena CorporationInventors: Junxian Weng, Christopher Kurowski, Sadok Aouini, Naim Ben-Hamida
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Patent number: 11483007Abstract: Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.Type: GrantFiled: June 23, 2021Date of Patent: October 25, 2022Assignee: Ciena CorporationInventors: Jerry Yee-Tung Lam, Douglas Stuart McPherson, Robert Gibbins, Naim Ben-Hamida
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Patent number: 11463093Abstract: Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A circuit, according to one implementation, includes a single Phase-Locked Loop (PLL) circuit having a main path and a return path forming a feedback loop. The circuit also includes one or more phase rotators connected to an output of the single PLL circuit outside the feedback loop and one or more adaptable Look-Up Tables (LUTs) populated with operating code to be provided to the one or more phase rotators for defining operating characteristics of the one or more phase rotators. Furthermore, the circuit includes a control device configured to receive phase response characteristics from the one or more phase rotators. The control device is further configured to modify the operating code of the one or more adaptable LUTs based on the phase response characteristics to reduce non-linearities of the one or more phase rotators.Type: GrantFiled: May 12, 2021Date of Patent: October 4, 2022Assignee: Ciena CorporationInventors: Jerry Yee-Tung Lam, Sadok Aouini, Naim Ben-Hamida
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Publication number: 20220254394Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Applicant: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski
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Publication number: 20220171425Abstract: Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.Type: ApplicationFiled: December 1, 2020Publication date: June 2, 2022Applicant: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson
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Patent number: 11349486Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.Type: GrantFiled: February 25, 2020Date of Patent: May 31, 2022Assignee: Ciena CorporationInventors: Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Ahmad Abdo, Mahdi Parvizi, Lukas Jakober
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Publication number: 20220149847Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.Type: ApplicationFiled: February 25, 2020Publication date: May 12, 2022Inventors: Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Ahmad Abdo, Mahdi Parvizi, Lukas Jakober