Patents by Inventor Nam-Jae Lee
Nam-Jae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230298992Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.Type: ApplicationFiled: May 19, 2023Publication date: September 21, 2023Applicant: SK hynix Inc.Inventors: Jin Won LEE, Nam Jae LEE
-
Publication number: 20230256429Abstract: A modular fluidic chip includes a body configured to have at least one flow channel formed in an inside thereof and be connected to another modular fluidic chip to allow the at least one flow channel to communicate with a flow channel provided in the other modular fluidic chip. A fluidic chip capable of performing one function is formed in the form of a module, whereby a fluidic flow system of various structures can be implemented without restriction in shape or size by connecting a plurality of fluidic chips capable of performing different functions as necessary. Through this, various and accurate experimental data can be obtained, and when a specific portion is deformed or damaged, only the fluidic chip corresponding thereto can be replaced, thereby reducing manufacture and maintenance costs.Type: ApplicationFiled: April 20, 2023Publication date: August 17, 2023Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Seok Jae LEE, Moon Keun LEE, Nam Ho BAE, Tae Jae LEE, Kyoung Gyun LEE, Yoo Min PARK
-
Publication number: 20230238437Abstract: A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.Type: ApplicationFiled: March 31, 2023Publication date: July 27, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Publication number: 20230232630Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack including interlayer insulating layers and word lines alternately stacked in a first direction, channel pillars passing through the gate stack and tapering toward the first direction, source select lines surrounding the channel pillars and extending to overlap the gate stack, and a source isolation insulating layer overlapping the gate stack between the source select lines and tapering toward a direction opposite to the first direction.Type: ApplicationFiled: February 28, 2023Publication date: July 20, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Publication number: 20230223457Abstract: The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Patent number: 11688682Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.Type: GrantFiled: October 13, 2021Date of Patent: June 27, 2023Assignee: SK hynix Inc.Inventors: Jin Won Lee, Nam Jae Lee
-
Publication number: 20230178485Abstract: A semiconductor device includes: a stack structure including conductive patterns and stack insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; a tunnel insulating layer surrounding the channel structure; a cell storage pattern surrounding the tunnel insulating layer; and a dummy storage pattern surrounding the tunnel insulating layer, the dummy storage pattern being spaced apart from the cell storage pattern. The conductive patterns include a select conductive pattern in contact with the tunnel insulating layer.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Patent number: 11666902Abstract: A modular fluidic chip includes a body configured to have at least one flow channel formed in an inside thereof and be connected to another modular fluidic chip to allow the at least one flow channel to communicate with a flow channel provided in the other modular fluidic chip. A fluidic chip capable of performing one function is formed in the form of a module, whereby a fluidic flow system of various structures can be implemented without restriction in shape or size by connecting a plurality of fluidic chips capable of performing different functions as necessary. Through this, various and accurate experimental data can be obtained, and when a specific portion is deformed or damaged, only the fluidic chip corresponding thereto can be replaced, thereby reducing manufacture and maintenance costs.Type: GrantFiled: July 25, 2019Date of Patent: June 6, 2023Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Seok Jae Lee, Moon Keun Lee, Nam Ho Bae, Tae Jae Lee, Kyoung Gyun Lee, Yoo Min Park
-
Patent number: 11661513Abstract: A thermoplastic resin composition according to the present invention comprises: about 100 parts by weight of a polycarbonate resin; about 5 to about 100 parts by weight of an inorganic filler; about 0.1 to about 2 parts by weight of a maleic anhydride-modified olefin-based copolymer; and about 0.1 to about 2 parts by weight of a phosphite compound represented by chemical formula 1. The thermoplastic resin composition is excellent in terms of chemical resistance, impact resistance, rigidity, physical property balance thereof, and the like.Type: GrantFiled: December 11, 2019Date of Patent: May 30, 2023Assignee: Lotte Chemical CorporationInventors: Nam Hyun Kim, Bong Jae Lee, Young Mi Kim, Ik Mo Kim, Sang Hwa Lee, Sang Hyun Hong
-
Patent number: 11658113Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.Type: GrantFiled: October 13, 2021Date of Patent: May 23, 2023Assignee: SK hynix Inc.Inventors: Jin Won Lee, Nam Jae Lee
-
Patent number: 11640976Abstract: A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.Type: GrantFiled: March 18, 2021Date of Patent: May 2, 2023Assignee: SK hynix Inc.Inventor: Nam Jae Lee
-
Patent number: 11637190Abstract: The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.Type: GrantFiled: January 28, 2021Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventor: Nam Jae Lee
-
Publication number: 20230120166Abstract: There are provided a semiconductor memory device and an erasing method of the semiconductor memory device. The semiconductor memory device includes: a plurality of word lines stacked between a source conductive pattern and a bit line; at least two drain select lines disposed between the plurality word lines and the bit line, the at least two drain select lines being spaced apart from each other in an extending direction of the bit line; and an erase control line disposed between the at least two drain select lines and the plurality of word lines.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Publication number: 20230115446Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor device includes: a first stack structure including interlayer insulating layers and first conductive patterns, which are alternately stacked; a second stack structure including a second conductive pattern overlapping with the first stack structure, and a third conductive pattern overlapping with the first stack structure with the second conductive pattern interposed between the first stack structure and the third conductive pattern, the third conductive pattern having an oxidation rate different from that of the second conductive pattern; channel structures penetrating the first stack structure and the second stack structure; and a bit line overlapping with the first stack structure with the second stack structure interposed between the first stack structure and the bit line.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Patent number: 11626419Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack including interlayer insulating layers and word lines alternately stacked in a first direction, channel pillars passing through the gate stack and tapering toward the first direction, source select lines surrounding the channel pillars and extending to overlap the gate stack, and a source isolation insulating layer overlapping the gate stack between the source select lines and tapering toward a direction opposite to the first direction.Type: GrantFiled: January 12, 2021Date of Patent: April 11, 2023Assignee: SK hynix Inc.Inventor: Nam Jae Lee
-
Publication number: 20230101919Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other; and a source contact structure extending into the stack structure in a vertical direction to be coupled to the source structure, wherein the source contact structure includes polysilicon.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Patent number: 11616074Abstract: The present disclosure provides a semiconductor device comprising: a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.Type: GrantFiled: April 27, 2020Date of Patent: March 28, 2023Assignee: SK hynix Inc.Inventor: Nam Jae Lee
-
Publication number: 20230085167Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a stacked body including alternately stacked interlayer insulating layers and conductive patterns, and channel structures penetrating the stacked body. Each of the channel structures may include a channel layer vertically extending up to the height of the upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns, a memory layer surrounding the channel layer and extending from the lower interlayer insulating layer to the height of the middle portion of the upper conductive pattern, and a doped semiconductor pattern disposed above the channel layer and the memory layer.Type: ApplicationFiled: November 22, 2022Publication date: March 16, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE
-
Patent number: 11594486Abstract: A semiconductor device includes: a stack structure including conductive patterns and stack insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; a tunnel insulating layer surrounding the channel structure; a cell storage pattern surrounding the tunnel insulating layer; and a dummy storage pattern surrounding the tunnel insulating layer, the dummy storage pattern being spaced apart from the cell storage pattern. The conductive patterns include a select conductive pattern in contact with the tunnel insulating layer.Type: GrantFiled: January 26, 2021Date of Patent: February 28, 2023Assignee: SK hynix Inc.Inventor: Nam Jae Lee
-
Publication number: 20230058892Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.Type: ApplicationFiled: November 7, 2022Publication date: February 23, 2023Applicant: SK hynix Inc.Inventor: Nam Jae LEE