Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.

Abstract: There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.

Abstract: Provided herein is a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a contact pattern including a vertical contact part, and a sidewall contact part extending from the vertical contact part in a direction crossing the vertical contact part, a lower conductive pattern having a hole into which the vertical contact part is inserted, and an upper conductive pattern overlapping a portion of the lower conductive pattern. The upper conductive pattern includes a first side portion in contact with the sidewall contact part, and a second side portion facing the vertical contact part and spaced apart from the vertical contact part.

Abstract: A semiconductor device may include a first gate structure including stacked first gate lines; first contact plugs extending through the first gate structure and connected to the first gate lines, respectively; a second gate structure including stacked second gate lines; second contact plugs extending through the second gate structure and connected to the second gate lines, respectively; and a slit structure located between the first gate structure and the second gate structure and including a lower sidewall having a wave shape and an upper sidewall having a straight line shape.

Abstract: A semiconductor device may include a gate structure including gate lines and insulating layers alternately stacked, a channel structure extending through the gate structure and including a channel layer and a channel pad connected to the channel layer, a dummy gate structure including stacked dummy gate lines, a dummy channel structure extending through the dummy gate structure and including a dummy channel layer and a dummy channel pad connected to the dummy channel layer, an isolation insulating layer disposed between the gate structure and the dummy gate structure, and a dummy pad disposed on the isolation insulating layer between the gate structure and the dummy gate structure.

Abstract: Disclosed is a method for manufacturing a semiconductor device, including: forming a first semiconductor structure comprising a logic transistor; forming a second semiconductor structure; bonding the first semiconductor structure to the second semiconductor structure, wherein forming the first semiconductor structure comprises: forming a first substrate; forming a first wiring layer comprising a plurality of first metal wirings and a plurality of first vias on the first substrate; forming a first bonding isolation layer on the first wiring layer, wherein forming the second semiconductor structure comprises: forming a second substrate; forming a second wiring layer comprising a plurality of second metal wirings and a plurality of second vias on the second substrate; forming a plurality of dummy plugs in the second wiring layer, forming a plurality of holes vertically penetrating the second substrate to a section in which the plurality of dummy plugs form, wherein the plurality of holes form after bonding the f

Abstract: A memory device, and a method of manufacturing the same, includes a gate stack formed on a cell region and a pass transistor region, a plurality of cell plugs extending in a vertical direction in the gate stack of the cell region, a plurality of gate contact structures extending in the vertical direction by passing through the gate stack of the pass transistor region, and a plurality of pass transistors connected to the plurality of respective gate contact structures. Each of the plurality of pass transistors has a cylindrical shape structure.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.

Abstract: A semiconductor device may include a stack structure having a plurality of semiconductor chips. Each of the plurality of semiconductor chips may have an interlayer insulating disposed over or on a substrate, a chip top interconnection disposed over or on the interlayer insulating layer and a chip top insulating layer disposed over or on the chip top interconnection. A side interconnection disposed over or on a side surface of the stack structure and connected to the chip top interconnection may be provided. A plurality of insulating patterns May be disposed between the stack structure and the side interconnection. Each of the plurality of insulating patterns may contact a side surface of the substrate and the interlayer insulating layer of adjacent one among the plurality of semiconductor chips.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The manufacturing method of the semiconductor memory device includes: forming a preliminary memory cell array that includes a gate stack structure and a channel structure wherein the gate stack structure includes interlayer insulating layers and conductive patterns, alternately stacked on a first substrate, and wherein the channel structure has a first end portion that penetrates the gate stack structure and extends into the first substrate; forming a common source line to be in contact with a second end portion of the channel structure, the common source line formed on a first surface of the gate stack structure; removing the first substrate; and forming a bit line connected to the first end portion of the channel structure on a second surface of the gate stack structure that is opposite of the first surface of the gate stack structure.

Abstract: Provided are a device for a digital assay of targets according to an exemplary embodiment of the present disclosure and a method using the same. The digital assay method of targets according to the exemplary embodiment of the present disclosure includes acquiring an image for a plurality of microdroplets, predicting at least one region based on the image for the plurality of microdroplets using an artificial neural network-based prediction model configured to segment at least one region among positive microdroplets, negative microdroplets, and atypical microdroplets, with the image for the plurality of microdroplets as an input, determining a number for the plurality of microdroplets based on the at least one region, and providing quantitative data of targets based on the number for the plurality of microdroplets.

Abstract: A memory device and a method of manufacturing the memory device includes a stacked structure having a cell region and a slimming region. The memory device also includes a plurality of vertical channel structures each including memory cells and vertically passing through the stacked structure in the cell region. The memory device further includes a plurality of support structures each having a structure of each of the vertical channel structures and vertically passing through the stacked structure in the slimming region. The plurality of support structures have different heights depending on the shape of the stacked structure in the slimming region.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor including: a plurality of source channels penetrating a source select line; a gate stack structure overlapping with the source select line; a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.

Abstract: The present disclosure relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a word line, a first select line on the word line, a second select line on the first select line, a first upper contact extending to be in contact with a first surface of the first select line, and a second upper contact extending through the second select line to be in contact with a second surface of the first select line, wherein the first surface and the second surface of the first select line are on opposites sides of each other.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a substrate with a complementary metal oxide semiconductor (CMOS) circuit; a gate stacked body with interlayer insulating layers and conductive patterns that are alternately stacked on the substrate in a vertical direction; a plurality of channel structures passing through the gate stacked body, each with a first end that protrudes above the gate stacked body; and a plurality of conductive layers disposed over the gate stacked body. Each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.

Abstract: A semiconductor device may include a gate structure including gate lines extending in a first direction; a first source pattern located on the gate structure; second source patterns located on the first source pattern and extending in a second direction intersecting the first direction; and channel structures extending through the gate structure and protruding into the first source pattern.

Abstract: A memory device, and a method of manufacturing the memory device, includes a lower structure including a first pad exposed through a top surface of the lower structure. The memory device also includes an upper structure including a second pad exposed through a bottom surface of the upper structure. The first and second pads are bonded to each other, and an interface at which the first and second pads are bonded to each other forms a curved surface.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.