Patents by Inventor Nam-Jae Lee

Nam-Jae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149053
    Abstract: A semiconductor memory device and a manufacturing method of a semiconductor memory device are described. The semiconductor memory device includes a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked, a first channel structure penetrating the gate stack structure, a first contact structure connected to the first channel structure, the first contact structure extending onto the gate stack structure, a bit line disposed on the first contact structure and being in contact with the first contact structure, a tunnel insulating layer disposed between the first channel structure and the gate stack structure, a data storage layer disposed between the tunnel insulating layer and the gate stack structure, and a blocking insulating layer disposed between the data storage layer and the gate stack structure, the blocking insulating layer extending between the first contact structure and the gate stack structure.
    Type: Application
    Filed: May 11, 2021
    Publication date: May 12, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220148961
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.
    Type: Application
    Filed: July 20, 2021
    Publication date: May 12, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Patent number: 11328981
    Abstract: The present disclosure includes a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate including a first area and a second area, a vertical insulating film passing through the substrate between the first area of the substrate and the second area of the substrate, an interlayer insulating structure disposed on the substrate, and a conductive pad formed on the interlayer insulating structure and overlapping the first area of the substrate. The semiconductor device &so includes a through electrode passing through the conductive pad, the interlayer insulating structure, and the substrate in the first area.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20220139930
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220139939
    Abstract: A semiconductor device includes a stacked body including a conductive pattern and an insulating pattern, a cell plug passing through the stacked body, a semiconductor layer, a peripheral transistor arranged on the semiconductor layer, a first conductor coupling the peripheral transistor to the cell plug, a second conductor coupled to the conductive pattern, a pass plug coupled to the second conductor, and a pass gate surrounding the pass plug, wherein the pass gate is arranged at substantially a same level as the semiconductor layer.
    Type: Application
    Filed: May 4, 2021
    Publication date: May 5, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Patent number: 11322518
    Abstract: A memory device and a method of manufacturing the memory device includes a stacked structure having a cell region and a slimming region therein and formed by alternately stacking insulating layers and conductive layers, vertical channel structures formed to pass through the stacked structure in the cell region, support structures formed to pass through the stacked structure in the slimming region, and having different heights depending on a stacked height of the slimming region, each of the support structures having the vertical channel structure, an etching prevention layer formed over the stacked structure and including carbon, and contact plugs formed to pass through the etching prevention layer and coupled to the conductive layers.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20220130855
    Abstract: A semiconductor device includes a first insulating layer, a first bonding pad in the first insulating layer, a second insulating layer in contact with the first insulating layer, and a second bonding pad in the second insulating layer. The first bonding pad includes a first conductive layer and a first barrier layer surrounding the first conductive layer, and the second bonding pad includes a second conductive layer and a second barrier layer surrounding the second conductive layer. The second barrier layer is in contact with the first conductive layer. The second conductive layer is spaced apart from the first conductive layer. The first conductive layer includes a metal material which is different from a metal material included in the second conductive layer. The first and second barrier layers each include at least one of titanium and tantalum.
    Type: Application
    Filed: April 27, 2021
    Publication date: April 28, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220130791
    Abstract: A semiconductor device includes a first insulating layer, wire contacts spaced apart from each other by the first insulating layer, and a bonding wire connected to the wire contacts. Each of the wire contacts includes a base part in the first insulating layer and a protrusion part protruding from inside to outside the first insulating layer. The protrusion parts of the wire contacts are in contact with the bonding wire.
    Type: Application
    Filed: April 28, 2021
    Publication date: April 28, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220123005
    Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes: a channel structure including a first pillar part and a second pillar part extending from the first pillar part; a blocking insulating layer surrounding a sidewall of the first pillar part; a data storage layer disposed between the first pillar part and the blocking insulating layer; an upper select line overlapping with an end portion of the blocking insulating layer and an end of the data storage layer, which face in an extending direction of the second pillar part, the upper select line surrounding a sidewall of the second pillar part; and a tunnel insulating layer disposed between the first pillar part and the data storage layer, the tunnel insulating layer extending between the second pillar part and the upper select line.
    Type: Application
    Filed: April 20, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220122916
    Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Nam-Kuk KIM, Nam-Jae LEE
  • Patent number: 11309286
    Abstract: A stack package includes first and second sub-chip stacks stacked on a package substrate and bonding wires. The first sub-chip stack includes first and second sub-chips. The first sub-chip has a first surface on which a first common pad is disposed. The second sub-chip has a third surface on which a second common pad is disposed. The third surface is bonded to the first surface such that the second common pad is bonded to the first common pad. The second sub-chip includes a fourth surface opposite to the second common pad and a through hole extending from the fourth surface to reveal the second common pad. The bonding wire is connected to the second common pad via the through hole and electrically connects both of the first and second common pads to the package substrate.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20220115056
    Abstract: A semiconductor memory device includes a substrate including a logic circuit, a memory cell array disposed over the substrate, a first conductive group including a plurality of bit lines and a first upper source line that are coupled to the memory cell array and spaced apart from each other and a first upper wire that is coupled to the logic circuit, an insulating structure covering the first conductive group.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Patent number: 11302626
    Abstract: A semiconductor memory device, and a method of manufacturing the same, includes: a gate stack structure including interlayer insulating layers and conductive patterns stacked in a first direction; a channel structure penetrating the gate stack structure; a peripheral contact plug spaced apart from the gate stack structure on a plane intersecting the channel structure, the peripheral contact plug extending in the first direction; and a capacitor spaced apart from the gate stack structure and the peripheral contact plug on the plane, the capacitor having an area wider than an area of the peripheral contact plug.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20220108994
    Abstract: A method of manufacturing a semiconductor memory device includes: forming a preliminary memory cell array on a support structure, the preliminary memory cell array with a stack structure and cell pillars; removing the support structure to expose a portion of each of the cell pillars; forming a protective layer that covers the exposed portion of each of the cell pillars; forming a mask pattern that exposes an opening defined between inclined surfaces of the protective layer wherein the inclined surfaces are disposed between the cell pillars; and etching at least one conductive layer among the conductive layers that is adjacent to the opening, thereby isolating the at least one conductive layer into select lines.
    Type: Application
    Filed: April 6, 2021
    Publication date: April 7, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Patent number: 11296021
    Abstract: A semiconductor memory device, and a method of manufacturing a semiconductor memory device, includes a stacked structure including a plurality of conductive layers for local lines stacked on a semiconductor substrate defined by a cell region and a slimming region to be spaced apart from each other, wherein the plurality of conductive layers for local lines are stacked in a step structure in the slimming region. The semiconductor memory device also includes a plurality of contact plugs formed to penetrate the stack structure in the slimming region, the plurality of contact plugs corresponding to each of the conductive layers for local lines. Each of the plurality of contact plugs includes a protrusion part protruding horizontally, and the protrusion part is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20220093635
    Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the first horizontal part; a first insulating pattern disposed between the first horizontal part and the second horizontal part of the first gate conductive pattern; and a second gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the second horizontal part of the second gate conductive pattern; a first gate contact structure extending vertically on a contact region, the first gate contact structure being in contact with the first gate conductive pattern while penetrating the third horizontal part of the first gate conductive pattern.
    Type: Application
    Filed: March 2, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220093637
    Abstract: A memory device and a respective manufacturing method are set forth, wherein the memory device includes: a peripheral circuit layer including a plurality of conductive pads; a bonding structure disposed on the peripheral circuit layer; a cell stack structure disposed on the bonding structure, the cell stack structure including a plurality of gate conductive patterns; and a plurality of vertical gate contact structures respectively connecting the plurality of conductive pads and the plurality of gate conductive patterns while penetrating the bonding structure, wherein each of the plurality of gate conductive patterns includes a first horizontal part and a second horizontal part, which extend horizontally from a cell region to a contact region, and a third horizontal part connected to one end of the first horizontal part and one end of the second horizontal part, the third horizontal part being connected to a corresponding gate contact structure.
    Type: Application
    Filed: March 17, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220093621
    Abstract: A semiconductor device is provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.
    Type: Application
    Filed: March 22, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220093756
    Abstract: A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.
    Type: Application
    Filed: March 18, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20220077163
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
    Type: Application
    Filed: November 16, 2021
    Publication date: March 10, 2022
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE