Patents by Inventor Nam-Jae Lee

Nam-Jae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350334
    Abstract: There are provided a semiconductor device and a method of manufacturing the same. A semiconductor device includes a memory block having local lines; a peripheral circuit disposed below the memory block; and a plurality of connection lines connecting the peripheral circuit and the local lines to each other, wherein the plurality of connection lines is stacked in a step shape.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventor: Nam Jae LEE
  • Publication number: 20200350168
    Abstract: A method of manufacturing a semiconductor device includes forming a first sacrificial layer including a nitride over a first source layer, forming a second sacrificial layer including aluminum oxide over the first sacrificial layer, forming a second source layer over the second sacrificial layer, forming a stacked structure over the second source layer, forming a channel layer that passes through the stacked structure, the second source layer, the second sacrificial layer, and the first sacrificial layer, the channel layer being enclosed by a memory layer, forming a slit that passes through the stacked structure and the second source layer, forming a polysilicon spacer in the slit, forming an opening by removing the first sacrificial layer and the second sacrificial layer, exposing the channel layer by etching the memory layer, and forming a third source layer in the opening.
    Type: Application
    Filed: October 18, 2019
    Publication date: November 5, 2020
    Inventors: Sun Young KIM, Nam Jae LEE
  • Publication number: 20200350249
    Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.
    Type: Application
    Filed: December 4, 2019
    Publication date: November 5, 2020
    Applicant: SK hynix Inc.
    Inventors: Nam-Kuk KIM, Nam-Jae LEE
  • Patent number: 10825824
    Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20200294850
    Abstract: A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.
    Type: Application
    Filed: October 9, 2019
    Publication date: September 17, 2020
    Inventor: Nam Jae LEE
  • Publication number: 20200286860
    Abstract: A stack package includes first and second sub-chip stacks stacked on a package substrate and bonding wires. The first sub-chip stack includes first and second sub-chips. The first sub-chip has a first surface on which a first common pad is disposed. The second sub-chip has a third surface on which a second common pad is disposed. The third surface is bonded to the first surface such that the second common pad is bonded to the first common pad. The second sub-chip includes a fourth surface opposite to the second common pad and a through hole extending from the fourth surface to reveal the second common pad. The bonding wire is connected to the second common pad via the through hole and electrically connects both of the first and second common pads to the package substrate.
    Type: Application
    Filed: October 2, 2019
    Publication date: September 10, 2020
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Patent number: 10770463
    Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
  • Patent number: 10756103
    Abstract: There are provided a semiconductor device and a method of manufacturing the same. A semiconductor device includes a memory block having local lines; a peripheral circuit disposed below the memory block; and a plurality of connection lines connecting the peripheral circuit and the local lines to each other, wherein the plurality of connection lines is stacked in a step shape.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20200258907
    Abstract: The present disclosure provides a semiconductor device comprising: a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventor: Nam Jae LEE
  • Publication number: 20200258900
    Abstract: A semiconductor device includes a first stepped structure including a first portion and a second portion, a second stepped structure including a third portion on the second portion of the first stepped structure, a first supporting structure penetrating the first portion of the first stepped structure, and a second supporting structure penetrating the second portion of the first stepped structure and the third portion of the second stepped structure. The first supporting structure includes a sidewall having a substantially constant slope, and the second supporting structure includes a sidewall having an inflection point.
    Type: Application
    Filed: August 27, 2019
    Publication date: August 13, 2020
    Inventor: Nam Jae LEE
  • Publication number: 20200237718
    Abstract: Provided is a method for treating a symptom of vibrio infection by using an RTX toxin production inhibitor comprising N-(4-oxo-4H-thieno[3,4-c]chromen-3-yl)-3-phenylprop-2-ynamide having derivatives thereof which can repress (prevent or treat) a symptom of vibrio infection by inhibiting RTX toxin production, other than directly killing vibrio bacteria, to not allow vibrio bacteria to have pathogenicity, and thereby can be an alternative to antibiotics that aim to kill bacteria themselves and thus fundamentally retain the problem of resistance incurrence.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 30, 2020
    Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Sang Ho CHOI, Lak Shin JEONG, Ho Jae HAN, Nam Chul HA, Byoung Sik KIM, Kyung Ku JANG, Zee-Won LEE
  • Publication number: 20200243546
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 30, 2020
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20200212064
    Abstract: The present disclosure relates to a semiconductor device having improved structural stability and a method of manufacturing such a semiconductor device. The semiconductor device includes a first stacked structure and a second stacked structure. The semiconductor device further includes a first support including a first upper pillar passing through the second stacked structure and including at least two first lower pillars extending from the first upper pillar and passing through the first stacked structure.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Publication number: 20200207979
    Abstract: A thermoplastic resin composition and a molded article formed of the same includes: about 100 parts by weight of a polycarbonate resin; about 1 to about 20 parts by weight of a rubber modified aromatic vinyl copolymer resin; about 0.1 to about 2 parts by weight of a maleic anhydride modified olefin copolymer; and about 0.1 to about 2 parts by weight of a phosphite compound represented by Formula 1 as described in the present specification. The thermoplastic resin composition can have good properties in terms of chemical resistance, impact resistance, and balance therebetween.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Inventors: Young Mi KIM, Nam Hyun KIM, Bong Jae LEE, Sang Hyun HONG
  • Patent number: 10701396
    Abstract: The present invention relates to a video encoding/decoding method and apparatus, and more particularly, to a method and apparatus for generating a reference image for a multiview video. The video encoding method includes, in the presence of a second image having a different view from a first image having a first view, transforming the second image to have the first view, generating a reference image by adding the second image to a side of the first image, and storing the reference image in a reference picture list.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: June 30, 2020
    Assignees: Electronics and Telecommunications Research Institute, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Gun Bang, Woo Woen Gwun, Gwang Soon Lee, Nam Ho Hur, Gwang Hoon Park, Sung Jae Yoon, Young Su Heo, Seok Jong Hong
  • Publication number: 20200203348
    Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.
    Type: Application
    Filed: March 5, 2020
    Publication date: June 25, 2020
    Inventors: Nam-gun KIM, Sang-min LEE, Tae-seop CHOI, Kon HA, Seung-jae LEE
  • Patent number: 10672786
    Abstract: The present disclosure provides a semiconductor device comprising: a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10665601
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Publication number: 20200144292
    Abstract: Provided herein is a semiconductor device including N stacked groups (where N is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and N concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the N concave portions each having stepped sidewalls being aligned in a first direction.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Patent number: RE48303
    Abstract: A refrigerator and a device for ice discharging are disclosed. The device for ice discharging includes a case having an ice introduction opening and an ice discharge opening (312); a rotation member (320) rotatable in the case to transfer ice that is held in a predetermined amount to be discharged; and a discharge adjustment part (340) spaced apart a predetermined space from the rotation member (320) to adjust the number of the ices transferred by the rotation member, such that a fixed amount of the ice is substantially discharged. The refrigerator includes the device for ice discharging therein.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 10, 2020
    Assignee: LG Electronics Inc.
    Inventors: Nam Gi Lee, Seong Jae Kim, Chang Ho Seo