Patents by Inventor Nam-Young Lee
Nam-Young Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961223Abstract: An apparatus for predicting performance of a wheel in a vehicle: includes a learning device that generates a latent space for a plurality of two-dimensional (2D) wheel images based on a convolutional autoencoder (CAE), extracts a predetermined number of the plurality of 2D wheel images from the latent space, and learns a dataset having the plurality of 2D wheel images and performance values corresponding to the plurality of 2D wheel images; and a controller that predicts performance for the plurality of 2D wheel images based on a performance prediction model obtained by the learning device.Type: GrantFiled: April 20, 2021Date of Patent: April 16, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, SOOKMYUNG WOMEN'S UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Jong Ho Park, Chang Gon Kim, Chul Woo Jung, Sang Min Lee, Min Kyoo Kang, Ji Un Lee, Kwang Hyeon Hwang, Nam Woo Kang, So Young Yoo, Seong Sin Kim, Sung Hee Lee
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Publication number: 20240120224Abstract: A semiconductor manufacturing equipment may include a process chamber for treating a substrate; a front-end module including a first transfer robot, wherein the first transfer robot may be configured to transport the substrate received in a container; a transfer chamber between the front-end module and the process chamber, wherein the transfer chamber may be configured to load or unload the substrate into or out of the process chamber; and a cassette capable of receiving a replaceable component capable of being used in the process chamber. The front-end module may include a seat plate configured to move in a sliding manner so as to retract or extend into or from the front-end module. The cassette may be configured to be loaded into the front-end module while the cassette is seated on the seat plate.Type: ApplicationFiled: September 12, 2023Publication date: April 11, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jin Hyuk CHOI, Beom Soo HWANG, Kong Woo LEE, Myung Ki SONG, Ja-Yul KIM, Kyu Sang LEE, Hyun Joo JEON, Nam Young CHO
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Patent number: 11943090Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.Type: GrantFiled: July 19, 2021Date of Patent: March 26, 2024Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung-Ik Park, Jae-Young Lee, Sun-Hyoung Kwon, Heung-Mook Kim, Nam-Ho Hur
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Publication number: 20240075922Abstract: A method for sensor fusion for a vehicle, includes determining a first point corresponding to a closest point of a target object from the vehicle with respect to a potential collision based on a LiDAR track thereof and a heading of the vehicle, determining a second point corresponding to a closest point of the target object from the vehicle with respect to a potential collision based on a sensor fusion track, and updating the sensor fusion track based on the first point and the second point.Type: ApplicationFiled: July 21, 2023Publication date: March 7, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Nam Hyung Lee, Bo Young Yun
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Patent number: 11923872Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.Type: GrantFiled: April 28, 2023Date of Patent: March 5, 2024Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
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Patent number: 9379227Abstract: A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.Type: GrantFiled: January 14, 2016Date of Patent: June 28, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hoon Lee, Chan-ho Park, Nam-young Lee
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Publication number: 20160126339Abstract: A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.Type: ApplicationFiled: January 14, 2016Publication date: May 5, 2016Inventors: Jae-hoon Lee, Chan-ho Park, Nam-young Lee
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Patent number: 9318586Abstract: According to example embodiments of inventive concepts: a semiconductor device includes: first and second trench gates extending long in one direction in a substrate; third and fourth trench gates in the substrate, the third and fourth trench gates connecting the first and second trench gates with each other; a first region defined in the substrate by the first to fourth trench gates and surrounded by the first to fourth trench gates; and a second region and a third region defined in the substrate. The second region is in surface contact with the first region. The third region is in point contact with the first region. The first region includes a first high-voltage semiconductor device including a body of a first conduction type and an emitter of a second conduction type in the body. Floating wells of the first conduction type are in the second region and the third region.Type: GrantFiled: August 23, 2013Date of Patent: April 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventor: Nam Young Lee
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Patent number: 9269790Abstract: A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.Type: GrantFiled: December 5, 2013Date of Patent: February 23, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hoon Lee, Chan-ho Park, Nam-young Lee
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Patent number: 9112010Abstract: A nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer.Type: GrantFiled: January 22, 2014Date of Patent: August 18, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-hoon Lee, Chan-ho Park, Nam-young Lee
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Patent number: 9048210Abstract: A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.Type: GrantFiled: July 16, 2012Date of Patent: June 2, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-su Jeong, Jai-kwang Shin, Nam-young Lee, Ji-hoon Lee, Min-kwon Cho, Yong-cheol Choi, Hyuk-soon Choi
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Patent number: 8967671Abstract: A bolting structure of a sub-frame includes a reinforcer mounting the sub-frame through a side member. The reinforcer includes: a reinforcing member disposed to intersect with the side member in a cross shape and bolted, together with the side member, to a lower panel; an inner pipe disposed at the side member from surfaces interfacing between the reinforcing member and the side member; an outer pipe disposed at the reinforcing member from the surfaces interfacing between the reinforcing member and the side member and inserted into the sub-frame; and a bolt bolted to the inner pipe through the outer pipe and fixing the sub-frame.Type: GrantFiled: March 13, 2013Date of Patent: March 3, 2015Assignee: Kia Motors CorporationInventors: Yong Dae Kim, Nam Young Lee, Seung Hyun Kang
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Publication number: 20140252368Abstract: A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.Type: ApplicationFiled: December 5, 2013Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-hoon Lee, Chan-ho Park, Nam-young Lee
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Publication number: 20140253241Abstract: A high electron mobility transistor (HEMT) device includes a buffer layer on a substrate; a face-inversion layer on a part of the buffer layer; a plurality of semiconductor layers on the face-inversion layer and on the buffer layer; and a source electrode, a drain electrode, and a gate electrode on the plurality of semiconductor layers. The HMT device has a stable, normally Off characteristic.Type: ApplicationFiled: November 12, 2013Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Lee, Chan-ho Park, Nam-young Lee
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Publication number: 20140252369Abstract: A nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer.Type: ApplicationFiled: January 22, 2014Publication date: September 11, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-hoon LEE, Chan-ho PARK, Nam-young LEE
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Publication number: 20140151991Abstract: A bolting structure of a sub-frame includes a reinforcer mounting the sub-frame through a side member. The reinforcer includes: a reinforcing member disposed to intersect with the side member in a cross shape and bolted, together with the side member, to a lower panel; an inner pipe disposed at the side member from surfaces interfacing between the reinforcing member and the side member; an outer pipe disposed at the reinforcing member from the surfaces interfacing between the reinforcing member and the side member and inserted into the sub-frame; and a bolt bolted to the inner pipe through the outer pipe and fixing the sub-frame.Type: ApplicationFiled: March 13, 2013Publication date: June 5, 2014Applicant: KIA MOTORS CORPORATIONInventors: Yong Dae KIM, Nam Young LEE, Seung Hyun KANG
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Publication number: 20140084332Abstract: According to example embodiments of inventive concepts: a semiconductor device includes: first and second trench gates extending long in one direction in a substrate; third and fourth trench gates in the substrate, the third and fourth trench gates connecting the first and second trench gates with each other; a first region defined in the substrate by the first to fourth trench gates and surrounded by the first to fourth trench gates; and a second region and a third region defined in the substrate. The second region is in surface contact with the first region. The third region is in point contact with the first region. The first region includes a first high-voltage semiconductor device including a body of a first conduction type and an emitter of a second conduction type in the body. Floating wells of the first conduction type are in the second region and the third region.Type: ApplicationFiled: August 23, 2013Publication date: March 27, 2014Inventor: Nam-Young LEE
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Publication number: 20130200427Abstract: A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.Type: ApplicationFiled: July 16, 2012Publication date: August 8, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-su Jeong, Jai-kwang Shin, Nam-young Lee, Ji-hoon Lee, Min-kwon Cho, Yong-cheol Choi, Hyuk-soon Choi
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Patent number: 8431990Abstract: A semiconductor device comprises a substrate and a gate which extends on the substrate in a first horizontal direction. A source region is positioned at a first side of the gate and extends in the first direction. A body region of a first conductivity type is under the source region and extends in the first direction. A drain region of a second conductivity type is at a second side of the gate and extends in the first direction. A drift region of the second conductivity type extends between the body region and the drain region in the substrate in a second horizontal direction. A first buried layer is under the drift region in the substrate, the first buried layer extending in the first and second directions. A plurality of second buried layers is between the first buried layer and the drift region in the substrate. The second buried layers extend in the second direction and are spaced apart from each other in the first direction.Type: GrantFiled: April 7, 2010Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Young Lee, Mueng-Ryul Lee
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Publication number: 20120286324Abstract: Provided is a manufacturing method for an insulated-gate bipolar transistor (IGBT). The manufacturing method includes providing a structure including a substrate, a first conductivity type epitaxial layer formed on the substrate, a gate electrode formed on a first surface of the epitaxial layer, a second conductivity type body region formed at opposite sides of the gate electrode in the first surface of the epitaxial layer, and a first conductivity type source region formed within the body region; removing a portion of the substrate by back grinding; and removing the other portion of the substrate by etching until the second surface of the epitaxial layer is exposed.Type: ApplicationFiled: April 5, 2012Publication date: November 15, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Nam-Young Lee