Patents by Inventor Naoaki Kokubun

Naoaki Kokubun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220075686
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta KUMANO, Hironori UCHIKAWA, Kosuke MORINAGA, Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE
  • Patent number: 11210163
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
  • Patent number: 11163639
    Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller converts a received value read from the nonvolatile memory into first likelihood information by using a first conversion table, executes decoding on the first likelihood information and outputting a posterior value, outputs an estimated value of the received value obtained on the basis of the posterior value in a case where the decoding is successful. The memory controller generates a second conversion table on the basis of the posterior value in a case where the decoding fails. The memory controller converts the received value into second likelihood information by using the second conversion table in a case where the second conversion table has been generated, and executes decoding on the second likelihood information and outputs a posterior value.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 2, 2021
    Assignee: Kioxia Corporation
    Inventors: Naoaki Kokubun, Daiki Watanabe
  • Publication number: 20210165713
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Publication number: 20210089393
    Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller converts a received value read from the nonvolatile memory into first likelihood information by using a first conversion table, executes decoding on the first likelihood information and outputting a posterior value, outputs an estimated value of the received value obtained on the basis of the posterior value in a case where the decoding is successful. The memory controller generates a second conversion table on the basis of the posterior value in a case where the decoding fails. The memory controller converts the received value into second likelihood information by using the second conversion table in a case where the second conversion table has been generated, and executes decoding on the second likelihood information and outputs a posterior value.
    Type: Application
    Filed: March 12, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Naoaki KOKUBUN, Daiki WATANABE
  • Patent number: 10956264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Publication number: 20200081770
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
  • Publication number: 20190377636
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Patent number: 10430275
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Publication number: 20190220348
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value read from the non-volatile memory to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: September 11, 2018
    Publication date: July 18, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE, Hironori UCHIKAWA
  • Publication number: 20190087264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Patent number: 10090860
    Abstract: A memory controller 2 of a memory system 1 according to an embodiment is provided with an encoding device 10 and a memory interface 5. The encoding device 10 is provided with an encoder 15 which generates a plurality of first parities by encoding a plurality of user data by using a common code, an interleaver 111 which sequentially interleaves the plurality of user data, and an XOR accumulator 112 which sequentially executes component-wise modulo-2 operation on the interleaved plurality of user data. The encoder 15 generates second parity by encoding a result finally obtained by executing the component-wise modulo-2 operation on a plurality of user data. The memory interface 5 writes a code word sequence including the plurality of user data, the first parities and the second parity in a non-volatile memory 9.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 2, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Naoaki Kokubun, Hironori Uchikawa
  • Publication number: 20170214415
    Abstract: A memory controller 2 of a memory system 1 according to an embodiment is provided with an encoding device 10 and a memory interface 5. The encoding device 10 is provided with an encoder 15 which generates a plurality of first parities by encoding a plurality of user data by using a common code, an interleaver 111 which sequentially interleaves the plurality of user data, and an XOR accumulator 112 which sequentially executes component-wise modulo-2 operation on the interleaved plurality of user data. The encoder 15 generates second parity by encoding a result finally obtained by executing the component-wise modulo-2 operation on a plurality of user data. The memory interface 5 writes a code word sequence including the plurality of user data, the first parities and the second parity in a non-volatile memory 9.
    Type: Application
    Filed: August 23, 2016
    Publication date: July 27, 2017
    Inventors: Naoaki Kokubun, Hironori Uchikawa
  • Publication number: 20160071597
    Abstract: According to an embodiment, a storage device includes a nonvolatile memory which includes a plurality of memory cells and a memory controller which controls writing on the nonvolatile memory. In a case where an exhaustion degree of the memory cell of the nonvolatile memory is less than a threshold, the memory controller performs a fractional-bit writing in which the number of threshold regions of the memory cell is set to Z (where, Z is a positive value not a power of two). In a case where the exhaustion degree of the memory cell is equal to or higher than the threshold, the memory controller performs an integer-bit writing in which the number of threshold regions of the memory cell is set to 2m (where, 2m is smaller than Z).
    Type: Application
    Filed: February 18, 2015
    Publication date: March 10, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoaki KOKUBUN, Osamu Torii, Riki Suzuki
  • Publication number: 20160055055
    Abstract: According to one embodiment, there is provided a memory system including a first generating unit, a buffer unit, a decoding unit, and an update unit. The first generating unit generates logarithm likelihood ratios for plural pieces of data read from a plurality of memory cells. The buffer unit stores the logarithm likelihood ratios. The decoding unit performs first error correction decoding process on the logarithm likelihood ratios, and estimates a logarithm likelihood ratio of data corresponding to an error memory cell among the plural pieces of read data. The update unit updates the logarithm likelihood ratios stored in the buffer unit using the estimated logarithm likelihood ratio.
    Type: Application
    Filed: February 19, 2015
    Publication date: February 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kohsuke HARADA, Naoaki KOKUBUN
  • Publication number: 20150311921
    Abstract: According to one embodiment, a memory controller includes a first decoder that decodes a block product code read out from a non-volatile memory and calculates reliability information of each sub-block, and an error cancellation unit that detects a sub-block having many errors based on the reliability information, and performs EXOR operation of a codeword in a column direction including the detected sub-block and a codeword in a row direction including the detected sub-block, and performs decoding using a result of the EXOR operation.
    Type: Application
    Filed: September 8, 2014
    Publication date: October 29, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Juan SHI, Osamu TORII, Naoaki KOKUBUN
  • Publication number: 20150310920
    Abstract: According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.
    Type: Application
    Filed: September 5, 2014
    Publication date: October 29, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoaki KOKUBUN, Osamu TORII, Kohsuke HARADA, Riki SUZUKI
  • Patent number: 9171629
    Abstract: According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoaki Kokubun, Osamu Torii, Kohsuke Harada, Riki Suzuki
  • Patent number: 9160371
    Abstract: According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G1 (x), generate a second parity group from second group data including third and fourth unit data using G1 (x), and generate a third parity group from the first and second group data and the first and second parity groups using G2 (x), a root of which continues form a root of G1 (x). The memory controller writes the first to fourth unit data and the first to third parity groups in different pages of a nonvolatile memory.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoaki Kokubun, Osamu Torii
  • Publication number: 20150254130
    Abstract: According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji SAKAUE, Kouji Saitou, Tatsuyuki Ishikawa, Kazuhiro Ichikawa, Naoaki Kokubun, Hironori Uchikawa