Patents by Inventor Naoaki Yamaguchi

Naoaki Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190232641
    Abstract: In an embodiment of the present invention, even though there is a print shift due to a gap between a nozzle in an upstream side and a nozzle in a downstream side of a printhead, a printing apparatus capable of precisely adjusting a slant of a printhead with respect to a conveyance direction in a nozzle surface of the printhead is provided. According to the embodiment, two adjustment patterns are printed at two different carriage speeds, respectively, and a print shift due to a slant of the nozzle surface of the printhead with respect to a conveyance direction of a print medium is adjusted based on these two print results.
    Type: Application
    Filed: January 23, 2019
    Publication date: August 1, 2019
    Inventors: Daigo Kuronuma, Masakazu Nagashima, Ryohei Maruyama, Tomohito Abe, Noriyuki Aoki, Naoaki Wada, Toshiaki Yamaguchi
  • Publication number: 20190232677
    Abstract: A liquid holding container includes a top face portion having an opening portion, a bottom face portion facing the top face portion, a first ink absorber being disposed near the opening portion and layered in a first direction from the bottom face portion to the top face portion, the first ink absorber being configured to absorb a liquid introduced from the opening portion, and a second ink absorber being disposed outside the first absorber in a second direction that intersects the first direction and layered in the second direction, the second ink absorber being configured to absorb the liquid moving from the first ink absorber.
    Type: Application
    Filed: January 10, 2019
    Publication date: August 1, 2019
    Inventors: Noriyuki Aoki, Masakazu Nagashima, Ryohei Maruyama, Toshiaki Yamaguchi, Naoaki Wada, Tomohito Abe, Daigo Kuronuma
  • Patent number: 10115970
    Abstract: A semi-solid electrode includes a first porous substrate and a second porous substrate stacked together to form a current collector, and a semi-solid electrode material embedded in the current collector. The semi-solid electrode material includes a suspension of an active material and a conductive material disposed in a non-aqueous liquid electrolyte. The porous substrates are at least partially disposed within the suspension such that the suspension substantially encapsulates the porous substrates. Each porous substrate in the current collector defines a pitch, and the two pitches of the two porous substrates in the current collector can be shifted with respect to each other by 30% to 70% of the pitch so as to reduce polarization effect.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: October 30, 2018
    Assignee: 24M Technologies, Inc.
    Inventors: Naoki Ota, Taison Tan, Takaaki Fukushima, Naoaki Yamaguchi, Hiromitsu Mishima
  • Patent number: 8273613
    Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Yasuhiko Takemura, Toshimitsu Konuma, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi
  • Patent number: 8198683
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: June 12, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Publication number: 20110068339
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Application
    Filed: December 2, 2010
    Publication date: March 24, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Toshimitsu KONUMA, Akira SUGAWARA, Yukiko UEHARA, Hongyong ZHANG, Atsunori SUZUKI, Hideto OHNUMA, Naoaki YAMAGUCHI, Hideomi SUZAWA, Hideki UOCHI, Yasuhiko TAKEMURA
  • Patent number: 7847355
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: December 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Patent number: 7749819
    Abstract: It is an object to obtain a crystalline silicon film having preferable characteristics for a thin film transistor. A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for crystallization; and further irradiating it with a laser light, thereby a crystalline silicon film having improved crystallinity can be obtained. By using the crystalline silicon film thus obtained, a semiconductor device such as a TFT having improved characteristic can be obtained.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi
  • Publication number: 20100068860
    Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
    Type: Application
    Filed: November 19, 2009
    Publication date: March 18, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hongyong ZHANG, Yasuhiko TAKEMURA, Toshimitsu KONUMA, Hideto OHNUMA, Naoaki YAMAGUCHI, Hideomi SUZAWA, Hideki UOCHI
  • Patent number: 7675060
    Abstract: Disclosed is a technique of improving the heat resistance of the aluminum gate electrode in bottom-gate-type TFT of which the active layer is made of a crystalline silicon film. A pattern of a laminate of a titanium film 102 and an aluminum film 103 is formed on a glass substrate 101. The pattern is to give a gate electrode 100. Then, the titanium film 102 is side-etched. Next, the layered substrate is heated to thereby intentionally form hillocks and whiskers on the surface of the aluminum pattern 103. Next, the aluminum pattern 103 acting as an anode is subjected to anodic oxidation to form an oxide film 105 thereon. The anodic oxidation extends to the lower edge of the aluminum pattern 103, at which the titanium layer was side-etched. Next, a gate-insulating film 106 and an amorphous silicon film are formed. A mask is formed over the pattern, which is to give the gate electrode, and then a nickel acetate solution is applied to the layered structure.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: March 9, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoaki Yamaguchi, Setsuo Nakajima
  • Patent number: 7635895
    Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: December 22, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Yasuhiko Takemura, Toshimitsu Konuma, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi
  • Publication number: 20090289254
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 26, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Patent number: 7569856
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: August 4, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Patent number: 7542103
    Abstract: An auxiliary capacitor for a pixel of an active matrix type liquid crystal display is provided without decreasing the aperture ratio. A transparent conductive film for a common electrode is formed under a pixel electrode constituted by a transparent conductive film with an insulation film provided therebetween. Further, the transparent conductive film for the common electrode is maintained at fixed potential, formed so as to cover a gate bus line and a source bus line, and configured such that signals on each bus line are not applied to the pixel electrode. The pixel electrode is disposed so that all edges thereof overlap the gate bus line and source bus line. As a result, each of the bus lines serves as a black matrix. Further, the pixel electrode overlaps the transparent conductive film for the common electrode to form a storage capacitor.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: June 2, 2009
    Assignee: Semiconductor Energy Laboratory
    Inventors: Hongyong Zhang, Naoaki Yamaguchi, Yasuhiko Takemura
  • Patent number: 7525158
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: April 28, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Patent number: 7504288
    Abstract: A linear laser light which has an energy and is to be scanned is irradiated to a semiconductor device formed on a substrate, and then the substrate is rotated to irradiate to the semiconductor device a linear laser light which has a higher energy than that of the irradiated linear laser light and is to be scanned. Also, in a semiconductor device having an analog circuit region and a remaining circuit region wherein the analog circuit region is smaller than the remaining circuit region, a linear laser light having an irradiation area is irradiated to the analog circuit region without moving the irradiation area so as not to overlap the laser lights by scanning. On the other hand, the linear laser light to be scanned is irradiated to the remaining circuit region.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: March 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoaki Yamaguchi, Yasuhiko Takemura
  • Patent number: 7381599
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 3, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Publication number: 20080020554
    Abstract: [Purpose] It is an object to obtain a crystalline silicon film having preferable characteristics for a thin film transistor. [Structure] A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for crystallization; and further irradiating it with a laser light, thereby a crystalline silicon film having improved crystallinity can be obtained. By using the crystalline silicon film thus obtained, a semiconductor device such as a TFT having improved characteristic can be obtained.
    Type: Application
    Filed: June 6, 2007
    Publication date: January 24, 2008
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi
  • Publication number: 20070182873
    Abstract: An auxiliary capacitor for a pixel of an active matrix type liquid crystal display is provided without decreasing the aperture ratio. A transparent conductive film for a common electrode is formed under a pixel electrode constituted by a transparent conductive film with an insulation film provided therebetween. Further, the transparent conductive film for the common electrode is maintained at fixed potential, formed so as to cover a gate bus line and a source bus line, and configured such that signals on each bus line are not applied to the pixel electrode. The pixel electrode is disposed so that all edges thereof overlap the gate bus line and source bus line. As a result, each of the bus lines serves as a black matrix. Further, the pixel electrode overlaps the transparent conductive film for the common electrode to form a storage capacitor.
    Type: Application
    Filed: April 16, 2007
    Publication date: August 9, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hongyong Zhang, Naoaki Yamaguchi, Yasuhiko Takemura
  • Patent number: 7235828
    Abstract: It is an object to obtain a crystalline silicon film having preferable characteristics for a thin film transistor. A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for crystallization; and further irradiating it with a laser light, thereby a crystalline silicon film having improved crystallinity can be obtained. By using the crystalline silicon film thus obtained, a semiconductor device such as a TFT having improved characteristic can be obtained.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 26, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi