Patents by Inventor Naohiro Hosoda

Naohiro Hosoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220270967
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a first metal oxide blocking dielectric layer, and a second metal oxide blocking dielectric layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the first metal oxide blocking dielectric layers and each of the electrically conductive layers.
    Type: Application
    Filed: May 12, 2022
    Publication date: August 25, 2022
    Inventors: Naohiro HOSODA, Masanori TSUTSUMI
  • Patent number: 11417621
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 16, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Masanori Tsutsumi, Sayako Nagamine
  • Publication number: 20220216145
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu UEDA
  • Patent number: 11367733
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: June 21, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Masanori Tsutsumi, Kota Funayama
  • Publication number: 20220181283
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Inventors: Naohiro HOSODA, Masanori TSUTSUMI, Sayako NAGAMINE
  • Publication number: 20220181343
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Inventors: Naohiro HOSODA, Masanori TSUTSUMI, Kota FUNAYAMA
  • Patent number: 11289416
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 29, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
  • Publication number: 20210159167
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu Yu UEDA
  • Patent number: 11018152
    Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: May 25, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Hinoue, Kengo Kajiwara, Ryousuke Itou, Naohiro Hosoda
  • Patent number: 11011506
    Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: May 18, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Kazuma Shimamoto, Tetsuya Shirasu, Yuji Fukano, Akio Nishida
  • Patent number: 10903237
    Abstract: Memory stack structures and dielectric wall structures are formed through a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers. Backside trenches are formed to divide the vertically alternating sequence into multiple alternating stacks. First portions of the continuous sacrificial material layers are replaced with electrically conductive layers. A connection region including a pair of dielectric wall structures is provided between a first memory array region and a second memory array region of a first alternating stack. Second portions of the continuous sacrificial material layers remain between the pair of dielectric wall structures as a vertical stack of dielectric plates. An upper subset of the first electrically conductive layers is patterned and is divided into multiple discrete portions. The multiple discrete portions are electrically connected by a respective set of connection metal interconnect structures.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 26, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Hiroyuki Ogawa, Yuki Mizutani
  • Publication number: 20210005627
    Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 7, 2021
    Inventors: Tatsuya HINOUE, Kengo KAJIWARA, Ryosuke ITOU, Naohiro HOSODA, Yohei MASAMORI, Kota FUNAYAMA, Keisuke TSUKAMOTO, Hirofumi WATATANI
  • Publication number: 20200258876
    Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
    Type: Application
    Filed: April 14, 2020
    Publication date: August 13, 2020
    Inventors: Naohiro HOSODA, Kazuma SHIMAMOTO, Tetsuya SHIRASU, Yuji FUKANO, Akio NISHIDA
  • Patent number: 10665580
    Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Kazuma Shimamoto, Tetsuya Shirasu, Yuji Fukano, Akio Nishida
  • Patent number: 10453798
    Abstract: A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Naohiro Hosoda
  • Patent number: 10347647
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Keisuke Shigemura, Junichi Ariyoshi, Kazuki Kajitani, Yuji Fukano
  • Publication number: 20190198515
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Naohiro HOSODA, Keisuke SHIGEMURA, Junichi ARIYOSHI, Kazuki KAJITANI, Yuji FUKANO
  • Publication number: 20190096808
    Abstract: A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA
  • Patent number: 10115730
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening and contacting a top surface of the semiconductor surface, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Naohiro Hosoda, Yanli Zhang, Raghuveer S. Makala, Hiroyuki Tanaka, Ryo Nakamura, Tadashi Nakamura
  • Patent number: 9978766
    Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 22, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Takeshi Kawamura, Yoko Furihata, Kota Funayama