Patents by Inventor Naohiro Hosoda
Naohiro Hosoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210005627Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.Type: ApplicationFiled: July 5, 2019Publication date: January 7, 2021Inventors: Tatsuya HINOUE, Kengo KAJIWARA, Ryosuke ITOU, Naohiro HOSODA, Yohei MASAMORI, Kota FUNAYAMA, Keisuke TSUKAMOTO, Hirofumi WATATANI
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Publication number: 20200258876Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.Type: ApplicationFiled: April 14, 2020Publication date: August 13, 2020Inventors: Naohiro HOSODA, Kazuma SHIMAMOTO, Tetsuya SHIRASU, Yuji FUKANO, Akio NISHIDA
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Patent number: 10665580Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.Type: GrantFiled: January 8, 2019Date of Patent: May 26, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Naohiro Hosoda, Kazuma Shimamoto, Tetsuya Shirasu, Yuji Fukano, Akio Nishida
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Patent number: 10453798Abstract: A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.Type: GrantFiled: September 27, 2017Date of Patent: October 22, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Masanori Tsutsumi, Naohiro Hosoda
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Patent number: 10347647Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.Type: GrantFiled: December 21, 2017Date of Patent: July 9, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Naohiro Hosoda, Keisuke Shigemura, Junichi Ariyoshi, Kazuki Kajitani, Yuji Fukano
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Publication number: 20190198515Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Naohiro HOSODA, Keisuke SHIGEMURA, Junichi ARIYOSHI, Kazuki KAJITANI, Yuji FUKANO
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Publication number: 20190096808Abstract: A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventors: Masanori TSUTSUMI, Naohiro HOSODA
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Patent number: 10115730Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening and contacting a top surface of the semiconductor surface, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure.Type: GrantFiled: June 19, 2017Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Ashish Baraskar, Naohiro Hosoda, Yanli Zhang, Raghuveer S. Makala, Hiroyuki Tanaka, Ryo Nakamura, Tadashi Nakamura
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Patent number: 9978766Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings.Type: GrantFiled: November 9, 2016Date of Patent: May 22, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Naohiro Hosoda, Takeshi Kawamura, Yoko Furihata, Kota Funayama
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Publication number: 20180130812Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings.Type: ApplicationFiled: November 9, 2016Publication date: May 10, 2018Inventors: Naohiro HOSODA, Takeshi KAWAMURA, Yoko FURIHATA, Kota FUNAYAMA
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Patent number: 9825049Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.Type: GrantFiled: January 16, 2016Date of Patent: November 21, 2017Assignee: Renesas Electronics CorporationInventors: Naohiro Hosoda, Daisuke Okada, Kozo Katayama
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Patent number: 9340352Abstract: To provide a water-soluble film roll 3 having end faces 4 with masking materials 5 adhered thereto. By using the water-soluble film roll 3 and paying out a water-soluble film 1 while holding the masking materials 5 adhered to the end faces 4, it is possible to prevent moisture from adhering to the end faces 4 and to prevent the water-soluble film 1 from rupturing due to welding of the film 1 with itself. In this connection, the masking materials 5 are preferably a plastic film capable of being adhered to the end faces 4 with a pressure-sensitive adhesive.Type: GrantFiled: January 6, 2012Date of Patent: May 17, 2016Assignee: KURARAY CO., LTD.Inventors: Naohiro Hosoda, Shintaro Hikasa
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Publication number: 20160133641Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.Type: ApplicationFiled: January 16, 2016Publication date: May 12, 2016Inventors: Naohiro HOSODA, Daisuke OKADA, Kozo KATAYAMA
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Patent number: 9245900Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.Type: GrantFiled: September 13, 2012Date of Patent: January 26, 2016Assignee: Renesas Electronics CorporationInventors: Naohiro Hosoda, Daisuke Okada, Kozo Katayama
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Publication number: 20130082315Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.Type: ApplicationFiled: September 13, 2012Publication date: April 4, 2013Inventors: Naohiro HOSODA, Daisuke OKADA, Kozo KATAYAMA
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Publication number: 20120121808Abstract: To provide a water-soluble film roll 3 having end faces 4 with masking materials 5 adhered thereto. By using the water-soluble film roll 3 and paying out a water-soluble film 1 while holding the masking materials 5 adhered to the end faces 4, it is possible to prevent moisture from adhering to the end faces 4 and to prevent the water-soluble film 1 from rupturing due to welding of the film 1 with itself. In this connection, the masking materials 5 are preferably a plastic film capable of being adhered to the end faces 4 with a pressure-sensitive adhesive.Type: ApplicationFiled: January 6, 2012Publication date: May 17, 2012Applicant: Kuraray Co., Ltd.Inventors: Naohiro HOSODA, Shintaro Hikasa
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Publication number: 20080293230Abstract: A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Inventors: Naohiro HOSODA, Kenji Kanamitsu
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Publication number: 20080233728Abstract: Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability.Type: ApplicationFiled: May 30, 2008Publication date: September 25, 2008Inventors: Naohiro HOSODA, Tetsuo Adachi
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Publication number: 20080226919Abstract: To provide a water-soluble film roll 3 having end faces 4 with masking materials 5 adhered thereto. By using the water-soluble film roll 3 and paying out a water-soluble film 1 while holding the masking materials 5 adhered to the end faces 4, it is possible to prevent moisture from adhering to the end faces 4 and to prevent the water-soluble film 1 from rupturing due to welding of the film 1 with itself. In this connection, the masking materials 5 are preferably a plastic film capable of being adhered to the end faces 4 with a pressure-sensitive adhesive.Type: ApplicationFiled: November 7, 2005Publication date: September 18, 2008Applicant: KURARAY CO., LTD.Inventors: Naohiro Hosoda, Shintaro Hikasa
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Patent number: 7419869Abstract: Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability.Type: GrantFiled: February 9, 2006Date of Patent: September 2, 2008Assignee: Renesas Technology Corp.Inventors: Naohiro Hosoda, Tetsuo Adachi