Patents by Inventor Naoki Esaka

Naoki Esaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250147691
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • Publication number: 20250123756
    Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 17, 2025
    Applicant: Kioxia Corporation
    Inventors: Koichi NAGAI, Naoki ESAKA, Toyohide ISSHI
  • Publication number: 20250068354
    Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 27, 2025
    Applicant: Kioxia Corporation
    Inventors: Hideki YOSHIDA, Shinichi KANNO, Naoki ESAKA
  • Patent number: 12229441
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: February 18, 2025
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 12223178
    Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: February 11, 2025
    Assignee: Kioxia Corporation
    Inventors: Koichi Nagai, Naoki Esaka, Toyohide Isshi
  • Publication number: 20250045200
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Application
    Filed: October 17, 2024
    Publication date: February 6, 2025
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Naoki ESAKA
  • Publication number: 20250013385
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA
  • Publication number: 20240427941
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes storage areas each configured to store user data. The controller acquires first information related to the number of program/erase cycles for at least one of the storage areas. In response to acquisition of the first information, the controller executes a data erase operation on each of the storage areas. In response to completion of the data erase operation, the controller acquires second information related to the number of program/erase cycles for the at least one of the storage areas. The controller generates an erase certificate that includes the first information and the second information.
    Type: Application
    Filed: September 3, 2024
    Publication date: December 26, 2024
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Yoshiyuki KUDOH
  • Patent number: 12175121
    Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: December 24, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Hideki Yoshida, Shinichi Kanno, Naoki Esaka
  • Publication number: 20240393946
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Patent number: 12147333
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: November 19, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Naoki Esaka
  • Patent number: 12124735
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: October 22, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Patent number: 12079473
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: September 3, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Naoki Esaka, Shinichi Kanno
  • Publication number: 20240086099
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Publication number: 20240061610
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • Patent number: 11899962
    Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores first data in the nonvolatile memory, performs a first transmission of a write request associated with the first data to the memory system, and stores management data including information equivalent to the write request in the nonvolatile memory. In response to receiving a first response to the write request transmitted in the first transmission, the CPU adds, to the management data, information indicating that the first response has been received. The CPU deletes the first data and the management data in response to receiving a second response to the write request transmitted in the first transmission after receiving the first response.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Koichi Nagai, Toyohide Isshi
  • Patent number: 11886727
    Abstract: According to one embodiment, a controller constructs a plurality of block groups. The plurality of block groups include at least a first block group configured using a first type block group and a second block group configured using a second block group. The first type block group includes a plurality of non-defective blocks obtained by selecting one or more non-defective blocks in an equal number from each of a plurality of dies or each of a plurality of planes. The second type block group includes a plurality of non-defective blocks. The number of non-defective blocks included in the second type block group is equal to the number of non-defective blocks included in the first type block.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: January 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Patent number: 11861202
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno
  • Patent number: 11861218
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: January 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 11836381
    Abstract: According to one embodiment, in response to receiving a first namespace create command specifying a first attribution from a host, a controller creates a first namespace having the first attribution and a first logical address range. The first logical address range includes logical addresses. The controller sets each of the logical addresses to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from a time when receiving a power loss advance notification or when detecting an unexpected power loss until a time when the controller becomes a ready state by resupply of a power to the memory system.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno