Patents by Inventor Naoki Makita
Naoki Makita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6987036Abstract: The invention is directed to a countermeasure against a local amorphous region observed as an eddy pattern on a thermally crystallized crystalline silicon film. The local amorphous region is thought to result from a deficiently formed ultra-thin silicon oxide film by ozone water treatment, which causes a local phenomenon of repelling a catalyst element solution during spin coating. This inhibits a uniform addition of a catalyst element. A relationship between an ozone concentration of ozone water and a wait time between the ozone water treatment and the subsequent step of adding the catalyst element is deduced and used for planning the countermeasure against the local amorphous region.Type: GrantFiled: August 1, 2002Date of Patent: January 17, 2006Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki-ku KaishaInventors: Toshiji Hamatani, Misako Nakazawa, Naoki Makita
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Publication number: 20060009015Abstract: A technique for manufacturing TFTs having little dispersion in their electrical characteristics is provided. Contamination of a semiconductor film is reduced by performing oxidation processing having an organic matter removing effect, forming a clean oxide film, after removing a natural oxide film formed on a semiconductor film surface. TFTs having little dispersion in their electrical characteristics can be obtained by using the semiconductor film thus obtained in active layers of the TFTs, and the electrical properties can be improved. In addition, deterioration in productivity and throughput can be reduced to a minimum by using a semiconductor manufacturing apparatus of the present invention.Type: ApplicationFiled: September 9, 2005Publication date: January 12, 2006Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Setsuo Nakajima, Aiko Shiga, Naoki Makita, Takuya Matsuo
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Patent number: 6951802Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.Type: GrantFiled: April 13, 2004Date of Patent: October 4, 2005Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
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Patent number: 6927107Abstract: In a production method of a semiconductor device, a catalyst element, e.g. Ni, is added to an amorphous silicon film, formed on a substrate with an insulating surface, for promoting crystallization of the amorphous silicon film. Thereafter, the amorphous silicon film is subjected to heat treatment to cause crystal growth therein. Next, the crystal growth is stopped in a state where minute amorphous regions (uncrystallized regions) remain in the film. Next, the silicon film is irradiated with strong light (laser light) so as to be further crystallized. As a result, a crystalline silicon film that has high quality and is excellent in uniformity is obtained.Type: GrantFiled: September 22, 2000Date of Patent: August 9, 2005Assignee: Sharp Kabushiki KaishaInventors: Naoki Makita, Hiromi Sakamoto, Masao Moriguchi
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Publication number: 20050170573Abstract: Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impurity and a higher concentration of p-type impurity, the gettering efficiency is inferior in a channel region of the n-channel transistor. Accordingly, the problem of inferior gettering efficiency in the n-channel TFT can be solved by providing at an end of its source/drain regions a highly efficient gettering region that contains an n-type impurity and a p-type impurity both with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.Type: ApplicationFiled: March 25, 2005Publication date: August 4, 2005Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Naoki Makita, Misako Nakazawa, Hideto Ohnuma, Takuya Matsuo
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Publication number: 20050151132Abstract: A barrier layer that meets three requirements, “withstand well against etching and protect a semiconductor film from an etchant as an etching stopper”, “allow impurities to move in itself during heat treatment for gettering”, and “have excellent reproducibility”, is formed and used to getter impurities contained in a semiconductor film. The barrier layer is a silicon oxide film and the ratio of a sub-oxide contained in the barrier layer is 18% or higher.Type: ApplicationFiled: February 3, 2005Publication date: July 14, 2005Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Mitsuhiro Ichijo, Toshiji Hamatani, Hideto Ohnuma, Naoki Makita
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Patent number: 6916693Abstract: In a crystallization process of an amorphous semiconductor film, a first crystalline semiconductor film having crystalline regions, and dotted with amorphous regions within the crystalline regions, is obtained by performing heat treatment processing after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. The amorphous regions are kept within a predetermined range by regulating the heat treatment conditions at this point. Laser annealing is performed on the first crystalline semiconductor film, to form a second crystalline semiconductor film. Electrical characteristics for a TFT manufactured based on the second crystalline semiconductor film can be obtained having less dispersion.Type: GrantFiled: March 5, 2001Date of Patent: July 12, 2005Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Hideto Ohnuma, Chiho Kokubo, Koichiro Tanaka, Naoki Makita, Shuhei Tsuchimoto
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Patent number: 6867077Abstract: A barrier layer that meets three requirements, “withstand well against etching and protect a semiconductor film from an etchant as an etching stopper”, “allow impurities to move in itself during heat treatment for gettering”, and “have excellent reproducibility”, is formed and used to getter impurities contained in a semiconductor film. The barrier layer is a silicon oxide film and the ratio of a sub-oxide contained in the barrier layer is 18% or higher.Type: GrantFiled: March 28, 2003Date of Patent: March 15, 2005Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Mitsuhiro Ichijo, Toshiji Hamatani, Hideto Ohnuma, Naoki Makita
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Patent number: 6835986Abstract: To manufacture a liquid crystal display device with high thin film transistor accumulation, high productivity and high reliability by efficiently gettering a catalyst element, which promotes crystallization of an amorphous silicon film, from a channel region. In order to solve the above object, a step of providing a gettering sink on the outside of a p-channel thin film transistor region, and a step of removing a region provided on the outside of the thin film transistor region within the region where the catalyst element is gettered in a self-aligning manner by a source wiring or a drain wiring, are combined.Type: GrantFiled: April 2, 2001Date of Patent: December 28, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Setsuo Nakajima, Naoki Makita
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Publication number: 20040192014Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.Type: ApplicationFiled: April 13, 2004Publication date: September 30, 2004Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
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Patent number: 6777713Abstract: By adding a novel improvement to the technique disclosed in JP 8-78329 A, a manufacturing method in which film characteristics of a semiconductor film having a crystalline structure are improved is provided. In addition, a TFT having superior TFT characteristics, such as field effect mobility, which uses the semiconductor film as an active layer, and a method of manufacturing the TFT, are also provided. A metallic element which promotes the crystallization of silicon is added to a semiconductor film having an amorphous structure and an oxygen concentration within the film of less than 5×1018/cm3. The semiconductor film having an amorphous structure is then heat-treated, forming a semiconductor film having a crystalline structure. Subsequently, an oxide film on the surface is removed. Oxygen is introduced to the semiconductor film having a crystalline structure, and processing is performed such that the concentration of oxygen within the film is from 5×1018/cm3 to 1×1021/cm3.Type: GrantFiled: October 8, 2002Date of Patent: August 17, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Hidekazu Miyairi, Aiko Shiga, Katsumi Nomura, Naoki Makita, Takuya Matsuo
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Publication number: 20040157413Abstract: By adding a novel improvement to the technique disclosed in JP 8-78329 A, a manufacturing method in which film characteristics of a semiconductor film having a crystalline structure are improved is provided. In addition, a TFT having superior TFT characteristics, such as field effect mobility, which uses the semiconductor film as an active layer, and a method of manufacturing the TFT, are also provided. A metallic element which promotes the crystallization of silicon is added to a semiconductor film having an amorphous structure and an oxygen concentration within the film of less than 5×1018/cm3. The semiconductor film having an amorphous structure is then heat-treated, forming a semiconductor film having a crystalline structure. Subsequently, an oxide film on the surface is removed. Oxygen is introduced to the semiconductor film having a crystalline structure, and processing is performed such that the concentration of oxygen within the film is from 5×1018/cm3 to 1×1021/cm3.Type: ApplicationFiled: February 5, 2004Publication date: August 12, 2004Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Hidekazu Miyairi, Aiko Shiga, Katsumi Nomura, Naoki Makita, Takuya Matsuo
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Patent number: 6770515Abstract: A TFT 123 formed on a glass substrate 101 has a crystalline silicon film 108 that serves as an active region. The crystalline silicon film 108 is formed by forming an a-Si film 103 containing hydrogen on the glass substrate 101, thereafter adding nickel 104 to the surface of the a-Si film 103 and subjecting the a-Si film 103 to which the nickel 104 has been added to heat treatment. The crystal grain size of each crystal of the crystalline silicon film 108 is smaller than the size of the channel region of a TFT 123. With this arrangement, a high-performance semiconductor device that has stable characteristics with little characteristic variation and a high integration density and is simply fabricated with high yield can be provided.Type: GrantFiled: September 12, 2000Date of Patent: August 3, 2004Assignee: Sharp Kabushiki KaishaInventors: Naoki Makita, Masao Moriguchi
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Publication number: 20040135180Abstract: A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the semiconductor layer, and a gate electrode arranged so as to oppose the channel region via the gate insulating film. At least a portion of the semiconductor layer includes a catalyst element capable of promoting crystallization, and the semiconductor layer further includes a gettering region that includes the catalyst element at a higher concentration than in the channel region or the source region and the drain region. The thickness of the gate insulating film on the gettering region is smaller than that on the source region and the drain region, or the gate insulating film is not disposed on the gettering region.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: SHARP KABUSHIKI KAISHAInventor: Naoki Makita
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Publication number: 20040124469Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivity of the channel region, wherein the surface of the semiconductor layer includes a minute protruding portion, and the side surface inclination angle of the gate electrode is larger than the inclination angle of the protruding portion of the semiconductor layer.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Applicant: Sharp Kabushiki KaishaInventor: Naoki Makita
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Patent number: 6756608Abstract: A semiconductor device which has satisfactory characteristics is provided. The semiconductor device includes a TFT manufactured by using a satisfactory crystalline semiconductor film and a circuit manufactured by using the TFT. An n-type impurity element (typically, phosphorous) is added to a gettering region of an n-channel TFT. A p-type impurity element (typically, boron) and a rare gas element (typically, argon) are added to a gettering region of a p-channel TFT. Then, there is performed heat treatment for gettering a catalytic element that remains in a semiconductor film.Type: GrantFiled: August 26, 2002Date of Patent: June 29, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Kenji Kasahara, Naoki Makita, Takuya Matsuo
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Publication number: 20040115906Abstract: A method of the present invention includes the steps of forming an amorphous semiconductor layer on an insulative surface, adding a catalyst element capable of promoting crystallization to the amorphous semiconductor layer and then performing a first heat treatment so as to crystallize the amorphous semiconductor layer, thereby obtaining a crystalline semiconductor layer, performing a first gettering process to remove the catalyst element from the semiconductor layer, and performing a second gettering process that is different from the first gettering process to remove the catalyst element from the semiconductor layer. The first gettering process includes removing at least large masses of a semiconductor compound of the catalyst element present in the crystalline semiconductor layer.Type: ApplicationFiled: November 3, 2003Publication date: June 17, 2004Applicant: Sharp Kabushiki KaishaInventors: Naoki Makita, Michinori Iwai, Shinya Morino, Takayuki Tsutsumi
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Patent number: 6734050Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.Type: GrantFiled: August 28, 2002Date of Patent: May 11, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
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Patent number: 6727124Abstract: A catalytic element for promoting crystallization of an amorphous silicon film is efficiently gettered to provide a highly reliable TFT, and an electro-optical device using the TFT and a method of manufacturing the electro-optical device are provided. The electro-optical device has an n-channel TFT and a p-channel TFT. A semiconductor layer of the p-channel TFT has a channel forming region (13), a region (11) containing an n-type impurity element and a p-type impurity element, and a region (12) containing only a p-type impurity element. In the p-channel TFT, a wiring line for electrically connecting the TFTs is connected to the region (12) containing only a p-type impurity element. The region containing an n-type impurity element in the p-channel TFT is narrower than a region doped with an n-type impurity element in a semiconductor layer of the n-channel TFT.Type: GrantFiled: November 2, 2001Date of Patent: April 27, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Setsuo Nakajima, Hideto Ohnuma, Naoki Makita, Takuya Matsuo
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Publication number: 20030201442Abstract: A semiconductor device includes at least one thin-film transistor, which includes a semiconductor layer, a gate electrode and a gate insulating film. In the semiconductor layer, a crystalline region, including a channel forming region, a source region and a drain region, is defined. The gate electrode is provided to control the conductivity of the channel forming region. The gate insulating film is provided between the gate electrode and the semiconductor layer. The semiconductor layer includes a gettering region outside of the crystalline region thereof.Type: ApplicationFiled: April 24, 2003Publication date: October 30, 2003Inventor: Naoki Makita