Patents by Inventor Naoki Saka

Naoki Saka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11810861
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: November 7, 2023
    Assignee: Sony Group Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 11658071
    Abstract: To more reliably suppress deterioration in characteristics due to signals (distortions) other than input and output waves while suppressing manufacturing cost. A semiconductor device according to the present disclosure includes a circuit substrate including an insulating film layer located above a predetermined semiconductor substrate and a semiconductor layer located above the insulating film layer, a plurality of passive elements provided on the circuit substrate and electrically connected with one another, and an electromagnetic shield layer locally provided in the insulating film layer corresponding to a portion where at least one of the plurality of passive elements is provided, and the electromagnetic shield layer and the semiconductor substrate are electrically separated from each other.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 23, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Naoki Saka
  • Publication number: 20220384349
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 1, 2022
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Publication number: 20220367536
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a concentration of electrically-conductive type impurities in a region on side of the first substrate is higher than a concentration of electrically-conductive type impurities in a region on side of the third substrate, in at least one or more semiconductor layers in which a field-effect transistor of the pixel circuit is provided.
    Type: Application
    Filed: June 25, 2020
    Publication date: November 17, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Naoki SAKA, Shintaro OKAMOTO, Yusuke KOHYAMA, Shigetaka MORI
  • Publication number: 20220367540
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate; a second substrate; and a through wiring line. The first substrate includes a photoelectric conversion section and a first transistor in a first semiconductor substrate. The photoelectric conversion section and the first transistor are included in a sensor pixel. The second substrate is stacked on the first substrate and includes a second transistor and an opening that extends through a second semiconductor substrate. The second substrate has an adjuster on at least one of a side surface of the opening near a gate of the second transistor or a region of a surface opposed to the first transistor. The second transistor is included in the sensor pixel. The adjuster adjusts a threshold voltage of the second transistor. The through wiring line is in the opening and electrically couples the first substrate and the second substrate.
    Type: Application
    Filed: June 25, 2020
    Publication date: November 17, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Naoki SAKA, Shigetaka MORI, Shintaro OKAMOTO, Shinji NAKAGAWA
  • Patent number: 11387185
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Sony Group Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 11355539
    Abstract: The present technology relates to a solid-state imaging apparatus and electronic equipment capable of coping with fluctuations in characteristics depending on the direction of current flow. There is provided a solid-state imaging apparatus including: a pixel array unit that includes pixels having a photoelectric conversion unit and arranged in a two-dimensional form, in which a transistor of the pixel has a structure in which an amount of overlap to an underside of a gate by a source-side LDD region differs from an amount of overlap to the underside of the gate by a drain-side LDD region, and a junction depth of the source-side LDD region differs from a junction depth of the drain-side LDD region. The present technology may be applied, for example, to a CMOS image sensor.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: June 7, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Naoki Saka
  • Publication number: 20210297619
    Abstract: The present technology relates to a solid-state imaging apparatus and electronic equipment capable of coping with fluctuations in characteristics depending on the direction of current flow. There is provided a solid-state imaging apparatus including: a pixel array unit that includes pixels having a photoelectric conversion unit and arranged in a two-dimensional form, in which a transistor of the pixel has a structure in which an amount of overlap to an underside of a gate by a source-side LDD region differs from an amount of overlap to the underside of the gate by a drain-side LDD region, and a junction depth of the source-side LDD region differs from a junction depth of the drain-side LDD region. The present technology may be applied, for example, to a CMOS image sensor.
    Type: Application
    Filed: July 23, 2019
    Publication date: September 23, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Naoki SAKA
  • Publication number: 20210066186
    Abstract: A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device, are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 4, 2021
    Applicant: SONY CORPORATION
    Inventor: Naoki SAKA
  • Publication number: 20210028113
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Application
    Filed: October 6, 2020
    Publication date: January 28, 2021
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 10879165
    Abstract: A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: December 29, 2020
    Assignee: Sony Corporation
    Inventor: Naoki Saka
  • Patent number: 10847466
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: November 24, 2020
    Assignee: Sony Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Publication number: 20200294857
    Abstract: To more reliably suppress deterioration in characteristics due to signals (distortions) other than input and output waves while suppressing manufacturing cost. A semiconductor device according to the present disclosure includes a circuit substrate including an insulating film layer located above a predetermined semiconductor substrate and a semiconductor layer located above the insulating film layer, a plurality of passive elements provided on the circuit substrate and electrically connected with one another, and an electromagnetic shield layer locally provided in the insulating film layer corresponding to a portion where at least one of the plurality of passive elements is provided, and the electromagnetic shield layer and the semiconductor substrate are electrically separated from each other.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 17, 2020
    Inventor: NAOKI SAKA
  • Publication number: 20200118928
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 16, 2020
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 10535607
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 14, 2020
    Assignee: Sony Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Publication number: 20180350744
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Publication number: 20180277479
    Abstract: A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer.
    Type: Application
    Filed: September 2, 2016
    Publication date: September 27, 2018
    Applicant: Sony Corporation
    Inventor: Naoki SAKA
  • Patent number: 10074610
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 11, 2018
    Assignee: Sony Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 9972751
    Abstract: A method for manufacturing a wavelength conversion member includes: forming a phosphor layer on a base body including phosphor particles and oxide particles affixed to surfaces of the phosphor particles; and forming a cover layer covering the surfaces of the phosphor particles and surfaces of the oxide particles continuously, and having a same oxide material as the oxide particles. A wavelength conversion member includes: a base body, a phosphor layer disposed on the base body and including phosphor particles and oxide particles affixed to surfaces of the phosphor particles; and a cover layer covering the surfaces of the phosphor particles and surfaces of the oxide particles continuously, and including a same oxide material as the oxide particles.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 15, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Naoki Saka, Jun Kawamata, Isamu Niki
  • Patent number: 9823557
    Abstract: A wavelength converting member includes at least a first, second, and third regions, circumferentially on a disc-shaped light-transmissive substrate. The first region includes, from a light incident direction, a first and second phosphor layers. The first phosphor layer includes a first phosphor to absorb at least part of incident light and to emit a first light having a wavelength different from the incident light. The first phosphor layer defines an indentation in a surface on the second phosphor layer side, with a depth a half or more of the thickness of a portion of the first phosphor layer absent of the indentation. The second phosphor layer includes a second phosphor to absorb at least part of the first light emitted by the first phosphor and to emit a second light having a wavelength different from the first light, and is disposed in the indentation of the first phosphor layer.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: November 21, 2017
    Assignee: Nichia Corporation
    Inventors: Naoki Saka, Yoshinori Murazaki, Isamu Niki