Patents by Inventor Naoki Takao

Naoki Takao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318320
    Abstract: The present invention provides a method of manufacturing an active element substrate aimed at reducing the production costs of an interlayer insulating film made from a spin-on glass material, for example. In the method of manufacturing an active element substrate, an interlayer insulating film is formed using a printing method that employs a plate. The plate includes: a main pattern that overlaps with signal lines that enclose openings; and fine line patterns that reduce, in the widthwise direction of the signal lines, the inclination of the edges of the printed pattern printed by the main pattern.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: April 19, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Daisuke Fuse, Masaya Yamamoto, Naoki Takao
  • Publication number: 20150294861
    Abstract: The present invention provides a method of manufacturing an active element substrate aimed at reducing the production costs of an interlayer insulating film made from a spin-on glass material, for example. In the method of manufacturing an active element substrate, an interlayer insulating film is formed using a printing method that employs a plate. The plate includes: a main pattern that overlaps with signal lines that enclose openings; and fine line patterns that reduce, in the widthwise direction of the signal lines, the inclination of the edges of the printed pattern printed by the main pattern.
    Type: Application
    Filed: October 21, 2013
    Publication date: October 15, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Daisuke Fuse, Masaya Yamamoto, Naoki Takao
  • Publication number: 20130029140
    Abstract: An outer packaging material for a battery or capacitor includes, a base layer, a barrier layer, an adhesive layer and a sealant layer which are sequentially laminated, has high adhesion between the barrier layer and the adhesive layer and is a good moisture barrier. The adhesive layer includes a maleic anhydride-modified polypropylene, wherein ? and ?, defined below, satisfy all the following conditions: ??0.09; ??10; and ???2.0; wherein a represents a ratio (A1790/A840) of a peak height (A1790) at 1790 cm-1 to a peak height (A840) at 840 cm-1 in infrared absorption spectrum of the maleic anhydride-modified polypropylene and ? represents a thickness of the adhesive layer in ?m.
    Type: Application
    Filed: April 7, 2011
    Publication date: January 31, 2013
    Applicant: OKURA INDUSTRIAL CO., LTD.
    Inventors: Naoki Takao, Yasunori Senoo, Masanao Orihara, Masamichi Oyama, Yukio Kouzai
  • Patent number: 6603071
    Abstract: An IC chip mounting FPC board of the present invention is provided with (1) a mounting region in a substantially quadrangular shape for mounting an IC chip, and (2) a plurality of inner-leads provided along each side of the mounting region, for being connected with the bumps of the IC chip so that the IC chip is mounted and bonded in the mounting region, in which the inner-leads is provided so as to have substantial equality between (a) a sum of areas of superimposing regions of the inner-leads provided on one of facing two sides, and (b) a sum of areas of superimposing regions of the inner-leads provided on the other of the facing two sides. Because this substantially equalizes the pressures applied on the respective inner-leads during the mounting of the IC chip, preventing the bonding pressure of the mounting from being unbalance, it is possible to provide an IC chip mounting FPC board having a high bonding reliability.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: August 5, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Naoki Takao
  • Publication number: 20020050381
    Abstract: An IC chip mounting FPC board of the present invention is provided with (1) a mounting region in a substantially quadrangular shape for mounting an IC chip, and (2) a plurality of inner-leads provided along each side of the mounting region, for being connected with the bumps of the IC chip so that the IC chip is mounted and bonded in the mounting region, in which the inner-leads is provided so as to have substantial equality between (a) a sum of areas of superimposing regions of the inner-leads provided on one of facing two sides, and (b) a sum of areas of superimposing regions of the inner-leads provided on the other of the facing two sides. Because this substantially equalizes the pressures applied on the respective inner-leads during the mounting of the IC chip, preventing the bonding pressure of the mounting from being unbalance, it is possible to provide an IC chip mounting FPC board having a high bonding reliability.
    Type: Application
    Filed: June 29, 2001
    Publication date: May 2, 2002
    Inventor: Naoki Takao