Patents by Inventor Naoki Yamamoto

Naoki Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11125231
    Abstract: A compressor includes a casing and a metallic coating. The casing includes a low-pressure casing part covering a low-pressure space and a high-pressure casing part covering a high-pressure space. The metallic coating is formed at least on a part of an outer surface of the casing. The metallic coating includes a low-pressure part coating formed in the low-pressure casing part, a high-pressure part coating formed in the high-pressure casing part, and a welded part coating formed in a welded part. At least either the average thickness of the low-pressure part coating or the average thickness of the welded part coating is greater than the average thickness of the high-pressure part coating.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: September 21, 2021
    Assignee: Daikin Industries, Ltd.
    Inventors: Naoki Shimozono, Mikio Kajiwara, Tomomi Yokoyama, Kouji Kojima, Tsuyoshi Fukunaga, Mahoba Ogawa, Yasuhiro Yamamoto
  • Publication number: 20210285449
    Abstract: A compressor assembly becomes a compressor as a result of a terminal guard being attached. The compressor assembly includes a body, and a terminal guard mounting seat attached to an outer surface of the body. The terminal guard is attachable to the terminal guard mounting seat. A compressor includes the compressor assembly and the terminal guard. The compressor can be manufactured by attaching the terminal guard mounting seat to the outer surface, administering metal spraying to at least part of the outer surface after attaching the terminal guard mounting seat, and attaching the terminal guard to the terminal guard mounting seat after the administering metal spraying.
    Type: Application
    Filed: July 25, 2017
    Publication date: September 16, 2021
    Inventors: Naoki SHIMOZONO, Mikio KAJIWARA, Tomomi YOKOYAMA, Kouji KOJIMA, Tsuyoshi FUKUNAGA, Mahoba OGAWA, Yasuhiro YAMAMOTO
  • Patent number: 11119372
    Abstract: A third metal wire, a common power supply line, a sensor power supply line, a selector switch 58, and a shield portion are provided. The third metal wire is provided on a first sensor electrode formed in a display region of an array substrate. The common power supply line and the sensor power supply line are provided in a peripheral region of the array substrate. The selector switch 58 is configured to supply either DC common voltage or AC sensor voltage to the first sensor electrode. The shield portion has a mesh shape. The shield portion is provided above the sensor power supply line. The shield portion is formed using the same material as the third metal wire.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 14, 2021
    Assignee: Japan Display Inc.
    Inventors: Koji Yamamoto, Hiroyuki Abe, Naoki Miyanaga
  • Publication number: 20210276427
    Abstract: A vehicle includes: two front wheels which are front right and left wheels and two rear wheels which are rear right and left wheels; a brake system capable of applying a braking force to only one of (a) the two front wheels and (b) two rear wheels, independently of each other utilizing a friction force; and a drive system configured to drive at least the other of (a) the two front wheels and (b) the two rear wheels by a force of electric, motors, each as a drive source, respectively corresponding to the other of (a) the two from wheels and (b) the two rear wheels, the drive system being capable of applying a braking force to at least the other of (a) the two front wheels and (b) the two rear wheels, independently of each other utilizing regeneration by the electric motors.
    Type: Application
    Filed: January 7, 2021
    Publication date: September 9, 2021
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki YAMAMOTO, Satoshi MURATA
  • Publication number: 20210277030
    Abstract: The present invention relates to compound (I) or a salt thereof which has a ROR?t inhibitory action. In the formula (I), each symbol is as defined in the specification.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Inventors: Satoshi Yamamoto, Junya Shirai, Mitsunori Kono, Yoshihide Tomata, Ayumu Sato, Atsuko Ochida, Yoshiyuki Fukase, Shoji Fukumoto, Tsuneo Oda, Hidekazu Tokuhara, Naoki Ishii, Yusuke Sasaki
  • Publication number: 20210265378
    Abstract: A manufacturing method of a semiconductor memory device in an embodiment, includes: forming a first mask pattern having a first opening and a plurality of second openings above a stacked body; forming a second mask pattern covering some of the plurality of second openings; and etching the stacked body with the first mask pattern as a mask while sequentially exposing the plurality of second openings by causing an end of the second mask pattern to retreat to form a first hole extending in the stacked body in a stacking direction of the stacked body at a position of the first opening and form a plurality of second holes extending in the stacked body to different depths in the stacking direction at positions of the plurality of second openings, and reaching first layers of a plurality of first layers at different levels.
    Type: Application
    Filed: September 1, 2020
    Publication date: August 26, 2021
    Applicant: Kioxia Corporation
    Inventors: Shunpei TAKESHITA, Naoki YAMAMOTO, Kojiro SHIMIZU
  • Patent number: 11101279
    Abstract: A semiconductor memory device includes: a substrate including a first and a second regions; first wiring layers disposed in a first direction; a second wiring layer; a third wiring layer closer to the substrate than the first and the second wiring layers; a semiconductor film that penetrates the first and the second wiring layers, and is connected to the third wiring layer; and a gate insulating film disposed between the semiconductor film and the first wiring layers. The first wiring layers include first conductive films opposed to the semiconductor film in the first region, and first films in the second region. The second wiring layer includes a second conductive film opposed to the semiconductor film in the first region, and a second film in the second region. The second film is different from the first films.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ken Komiya, Takamasa Ito, Naoki Yamamoto, Yu Hirotsu, Kazuhiro Tomishige, Yoshinori Nakakubo
  • Publication number: 20210244925
    Abstract: A method of producing a microneedle sheet according to an embodiment includes: preparing a sheet having a first surface and a second surface; making a first cut in a range from the first surface to the second surface of the sheet to form a first outer edge that defines a tip end of the microneedle; and making, after forming the first outer edge, a second cut in a range from the first surface to the second surface of the sheet to form a second outer edge that defines the tip end of the microneedle, thereby forming the tip end of the microneedle.
    Type: Application
    Filed: July 11, 2019
    Publication date: August 12, 2021
    Inventors: Eisuke HATANAKA, Kazuki KURIYAMA, Naoki YAMAMOTO
  • Publication number: 20210233895
    Abstract: A semiconductor storage device includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and penetrating the plurality of conductive layers. The plurality of conductive layers includes a first conductive layer and a second conductive layer that are adjacent to each other, a third conductive layer and a fourth conductive layer that are adjacent to each other, and a fifth conductive layer and a sixth conductive layer that are adjacent to each other.
    Type: Application
    Filed: August 31, 2020
    Publication date: July 29, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Masashi YAMAOKA, Kazuhiro TOMISHIGE, Naoki YAMAMOTO
  • Patent number: 11041220
    Abstract: Provided is a blast furnace operation method that enables lowering of the reducing agent ratio of a blast furnace. The blast furnace operation method includes injecting pulverized coal through tuyeres of a blast furnace. The method includes adjusting coal containing moisture and volatile matter to form adjusted pulverized coal having a specific surface area within a range of 2 m2/g or more and 1000 m2/g or less, a lower heating value of 27170 kJ/kg or more, and a volatile matter content within a range of 3 mass % or more and 25 mass % or less. The method further includes injecting, through the tuyeres of the blast furnace, pulverized coal in which the adjusted pulverized coal, in a mixing ratio of 10 mass % or more, is mixed.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 22, 2021
    Assignee: JFE Steel Corporation
    Inventors: Naoki Yamamoto, Akinori Murao, Kota Moriya, Nobuyuki Oyama
  • Patent number: 11035623
    Abstract: Provided is a heat exchanger which includes: multiple heat transfer pipes in which refrigerant flows; and a corrugated fin joined to the heat transfer pipes; and multiple plate-shaped fins. The plate-shaped fins are joined to at least one of each heat transfer pipe or the corrugated fin, and are arranged on a windward side in an air blowing direction with respect to the corrugated fin such that a plate width direction of each plate-shaped fin is substantially coincident with a plate width direction of the corrugated fin.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 15, 2021
    Assignee: HITACHI-JOHNSON CONROLS AIR CONDITIONING, INC.
    Inventors: Takumi Hirata, Mamoru Houfuku, Ryoichi Takafuji, Kosuke Kumamoto, Naoki Yamamoto
  • Patent number: 11007358
    Abstract: A microneedle sheet is disclosed that comprises a plurality of microneedles formed on a sheet generally along a principal surface of the sheet, wherein the microneedles contain a water-soluble polysaccharide and water, the water content is 1 mass % or more and less than 19 mass % based on the total mass of the microneedles, and the microneedles are raised from the principal surface by bending the sheet.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 18, 2021
    Assignee: HISAMITSU PHARMACEUTICAL CO., INC.
    Inventors: Naoki Yamamoto, Seiji Tokumoto
  • Patent number: 10995930
    Abstract: A rear light is a light disposed in a rear portion of a vehicle, and includes: a light source; a light-transmitting plate that guides incident light from the light source; and a dot portion that is disposed on the light-transmitting plate and reflects incident light to the outside of the vehicle with different reflection intensities depending on positions on the light-transmitting plate.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 4, 2021
    Assignee: MAZDA MOTOR CORPORATION
    Inventors: Naoki Yamamoto, Yoshiaki Nakaya, Toshiaki Wakabayashi, Takahiro Yamamoto
  • Patent number: 10987502
    Abstract: The microneedle sheet according to an embodiment comprises a plurality of microneedles formed on a sheet generally along a main surface of the sheet; a bending resistance of the sheet as measured in accordance with a 45° cantilever method defined by JIS L 1096:2010 is 4.2 cm to 12.5 cm; and a material of the sheet is a biodegradable polymer. The microneedles rise from the main surface when the sheet is bent, and the raised microneedles pierce the skin.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 27, 2021
    Assignee: HISAMITSU PHARMACEUTICAL CO., INC.
    Inventors: Ryusuke Fudoji, Naoki Yamamoto
  • Patent number: 10964711
    Abstract: A semiconductor memory device includes a first insulating layer over a semiconductor substrate, a metal layer, an adhesive layer on a first region of the metal layer, a conductive layer on a second region of the metal layer and on the adhesive layer, a second insulating layer on the conductive layer, a plurality of wiring layers that are separated from each other and are stacked above the second insulating layer, a semiconductor layer that extends in a first direction perpendicular to the semiconductor substrate and includes a bottom surface connected to the conductive layer, a storage portion disposed between at least one of the plurality of wiring layers and the semiconductor layer, and a slit that extends in the first direction, includes aside surface in contact with the plurality of wiring layers and a bottom surface reaching the conductive layer, and is filled with an insulating material.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Murata, Yoshinori Nakakubo, Hiroaki Hayasaka, Naoki Yamamoto
  • Patent number: 10964044
    Abstract: In a method of operating a measurement device, an image acquisition unit acquires a first image of a subject. A display control unit displays the first image or a second image regarding the first image on a display. A reading unit reads one or more pieces of reference information from a storage medium. The reference information represents two reference positions on the subject. The display control unit displays the one or more pieces of reference information on the display. A setting unit sets two reference positions on the first image or the second image after the first image or the second image is displayed on the display and the reference information is displayed on the display.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 30, 2021
    Assignee: OLYMPUS CORPORATION
    Inventor: Naoki Yamamoto
  • Publication number: 20210088537
    Abstract: Disclosed is a method for measuring activated partial thromboplastin time, the method comprising: mixing: a blood sample; a first reagent comprising an ellagic acid compound and a compound represented by Formula (I); and a second regent comprising a calcium ion; and measuring activated partial thromboplastin time using the mixture prepared in the mixing step, wherein the compound represented by Formula (I) is shown below wherein X is a hydrogen atom, —(C?O)—Y, or —(C?O)—OZ, Y is a hydroxyl group, a hydrogen atom, a linear or branched alkyl group having a carbon number of 1 or more and 6 or less, or a phenyl group, and Z is an alkali metal.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 25, 2021
    Applicant: SYSMEX CORPORATION
    Inventors: Takahiko BANDO, Kohei AKATSUCHI, Naoki YAMAMOTO, Masako AKI, Hiroshi NEGORO, Masato MICHISHITA
  • Patent number: 10942134
    Abstract: A reference designation point setting unit sets a plurality of reference designation points. A reference calculation unit calculates one of a reference line and a reference plane used in a measurement mode indicated by measurement mode information, on the basis of the plurality of reference designation points. A measurement point setting unit sets a measurement point. A reference point calculation unit calculates a plurality of reference points leading to higher reliability of a measurement result instead of a plurality of reference designation points, on the basis of the image in which the measurement point is set, the plurality of reference designation points, the measurement mode, and the measurement point. The reference calculation unit calculates one of a new reference line and a new reference plane on the basis of the plurality of reference points.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: March 9, 2021
    Assignee: OLYMPUS CORPORATION
    Inventor: Naoki Yamamoto
  • Patent number: 10916557
    Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shunpei Takeshita, Namiki Yoshikawa, Kazuhide Takamura, Naoki Yamamoto
  • Publication number: 20210009250
    Abstract: The aim of the present invention is to provide a processing device and a processing method, with which it is possible to improve processing accuracy. A processing device processes a work piece which integrally includes a plate-shaped first curved-surface section and a plate-shaped planar-surface section that extends from the edge of the first curved-surface section in a bending manner. Furthermore, the processing device includes a first clamp device which includes a contact part that makes contact with the first curved-surface section, and a pressing part that presses the first curved-surface section in the direction of the contact part, and which restricts movement of the first curved-surface section in the plate thickness direction; a second clamp device which is movable in the plate thickness direction of the planar-surface section and supports the planar-surface section; and a machining device which machines the first curved-surface section.
    Type: Application
    Filed: April 18, 2019
    Publication date: January 14, 2021
    Inventors: Takeshi YAMADA, Tetsunori MIYOSHI, Akira KITANO, Masahiro AOYAMA, Takeshi KADOMASU, Yuya TANAKA, Naoki YAMAMOTO