Patents by Inventor Naoki Yoshimatsu

Naoki Yoshimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707141
    Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Osamu Usui, Yuji Imoto
  • Publication number: 20200098701
    Abstract: A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).
    Type: Application
    Filed: February 9, 2017
    Publication date: March 26, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki HARADA, Naoki YOSHIMATSU, Osamu USUI, Yuji IMOTO, Yuki YOSHIOKA
  • Publication number: 20190285246
    Abstract: A light emitting device includes: a light emitting element; a reflection wall that surrounds the light emitting element; and a diffusion reflection sheet that includes a plurality of particles and permits entrance of emitted light from the light emitting element and reflected light from the reflection wall.
    Type: Application
    Filed: July 25, 2017
    Publication date: September 19, 2019
    Applicant: Sony Corporation
    Inventors: Takeshi Yamamoto, Tomoyuki Yoshimatsu, Soya Araki, Naoki Tanaka
  • Publication number: 20190267297
    Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).
    Type: Application
    Filed: October 24, 2016
    Publication date: August 29, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoki YOSHIMATSU, Osamu USUI, Yuji IMOTO
  • Patent number: 10104775
    Abstract: A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 16, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Masayoshi Shinkai, Taketoshi Shikano, Daisuke Murata, Nobuyoshi Kimoto, Yuji Imoto, Mikio Ishihara
  • Patent number: 10038901
    Abstract: An image encoding method includes: selecting, for each processing block, one of intra prediction modes specified by a coding standard, and performing intra prediction according to the intra prediction mode, wherein the intra prediction modes include a lower-left reference mode in which a processing block located at lower left of a current processing block is referred to, the processing blocks include a first processing block and a second processing block located at upper right of the first processing block, the second processing block being equal in size to the first processing block, the coding standard defines that information on the second processing block is written into a bitstream after information on the first processing block.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 31, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Sakakibara, Kiyofumi Abe, Naoki Yoshimatsu, Hideyuki Ohgose, Koji Arimura, Hiroshi Arakawa, Kazuhito Kimura
  • Publication number: 20170302919
    Abstract: An image encoding method includes: selecting, for each processing block, one of intra prediction modes specified by a coding standard, and performing intra prediction according to the intra prediction mode, wherein the intra prediction modes include a lower-left reference mode in which a processing block located at lower left of a current processing block is referred to, the processing blocks include a first processing block and a second processing block located at upper right of the first processing block, the second processing block being equal in size to the first processing block, the coding standard defines that information on the second processing block is written into a bitstream after information on the first processing block, and in the intra prediction, (i) selection of the lower-left reference mode is prohibited and intra prediction is performed on the second processing block, and, (ii) intra prediction is performed on the first processing block.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 19, 2017
    Inventors: Kazuma SAKAKIBARA, Kiyofumi ABE, Naoki YOSHIMATSU, Hideyuki OHGOSE, Koji ARIMURA, Hiroshi ARAKAWA, Kazuhito KIMURA
  • Patent number: 9735100
    Abstract: A semiconductor device according to the present invention includes a plurality of semiconductor chips, a plate electrode disposed on the plurality of semiconductor chips for connecting the plurality of semiconductor chips, and an electrode disposed on the plate electrode. The electrode has a plurality of intermittent bonding portions to be bonded to the plate electrode and a protruded portion which is protruded erectly from the bonding portions. The protruded portion has an ultrasonic bonding portion which is parallel with the bonding portion and is ultrasonic bonded to an external electrode.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: August 15, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Ishibashi, Yoshihiro Yamaguchi, Naoki Yoshimatsu, Hidehiro Koga
  • Patent number: 9723326
    Abstract: An image encoding method includes: selecting, for each processing block, one of intra prediction modes specified by a coding standard, and performing intra prediction according to the intra prediction mode, wherein the intra prediction modes include a lower-left reference mode in which a processing block located at lower left of a current processing block is referred to, the processing blocks include a first processing block and a second processing block located at upper right of the first processing block, the second processing block being equal in size to the first processing block, the coding standard defines that information on the second processing block is written into a bitstream after information on the first processing block, and in the intra prediction, (i) selection of the lower-left reference mode is prohibited and intra prediction is performed on the second processing block, and, (ii) intra prediction is performed on the first processing block.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: August 1, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Sakakibara, Kiyofumi Abe, Naoki Yoshimatsu, Hideyuki Ohgose, Koji Arimura, Hiroshi Arakawa, Kazuhito Kimura
  • Patent number: 9698091
    Abstract: A power semiconductor device includes an insulating substrate, a semiconductor element, a case, and a wiring member. The case forms a container body having a bottom surface defined by a surface of the insulating substrate, to which said semiconductor element is bonded. The wiring member has a bonding portion positioned above an upper surface electrode of the semiconductor element. The bonding portion of the wiring member is provided with a projection portion projecting toward the upper surface electrode of the semiconductor element and bonded to the upper surface electrode with a solder, and a through hole passing through the bonding portion in a thickness direction through the projection portion.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 4, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinsuke Asada, Naoki Yoshimatsu, Yuji Imoto, Yusuke Ishiyama, Junji Fujino
  • Patent number: 9691730
    Abstract: A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 27, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Yusuke Ishiyama, Taketoshi Shikano, Yuji Imoto, Junji Fujino, Shinsuke Asada
  • Patent number: 9455215
    Abstract: A semiconductor device includes a conductive portion having semiconductor elements provided on a substrate, a case housing the conductive portion, and a lead terminal integrated into the case to be directly connected to the semiconductor elements or an interconnection of the substrate. The lead terminal has a stress relief shape for reliving stress generated in the lead terminal.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: September 27, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Imoto, Naoki Yoshimatsu, Junji Fujino
  • Patent number: 9437460
    Abstract: Entry of resin into a cylindrical electrode can be suppressed without excessively increasing the number of parts and without unnecessarily damaging members. For this purpose, a semiconductor chip and a cylindrical electrode are mounted on one main surface of substrate. The substrate, the semiconductor chip, and the cylindrical electrode are sealed with resin material such that the cylindrical electrode has one end mounted to the substrate and the other opposite end at least exposed. After the step of sealing, an opening extending from the other end of the cylindrical electrode to a cavity in the cylindrical electrode is formed. Before performing the step of forming an opening, the other end of the cylindrical electrode is closed.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 6, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Kiyohiro Uchida, Taketoshi Shikano, Masayoshi Shinkai
  • Patent number: 9418910
    Abstract: A circuit pattern is bonded to a top surface of a ceramic substrate. A cooling body is bonded to an undersurface of the ceramic substrate. An IGBT and a FWD are provided on the circuit pattern. A coating film covers a junction between the ceramic substrate and the circuit pattern, and a junction between the ceramic substrate and the cooling body. A mold resin seals the ceramic substrate, the circuit pattern, the IGBT, the FWD, the cooling body, and the coating film etc. The ceramic substrate has higher thermal conductivity than the coating film. The coating film has lower hardness than the mold resin and alleviates stress applied from the mold resin to the ceramic substrate. The circuit pattern and the cooling body includes a groove contacting the mold resin without being covered with the coating film.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: August 16, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noboru Miyamoto, Naoki Yoshimatsu
  • Publication number: 20160111345
    Abstract: A base plate (1) includes a fixed surface and a radiating surface which is a surface opposite to the fixed surface. An insulating substrate (3) is bonded to the fixed surface of the base plate (1). Conductive patterns (4,5) are provided on the insulating substrate (3). Semiconductor chips (7,8) are bonded to the conductive pattern (4). An Al wire (12) connects top surfaces of the semiconductor chip (8) to the conductive pattern (5). The insulating substrate (3), the conductive patterns (4 ,5), the semiconductor chips (7 to 10) and the Al wires (11 to 13) are sealed with resin (16). The base plate (1) includes a metal part (19) and a reinforcing member (20) provided in the metal part (19). A Young's modulus of the reinforcing member (20) is higher than a Youngs modulus of the metal part (19).
    Type: Application
    Filed: August 29, 2013
    Publication date: April 21, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tatsuya KAWASE, Noboru MIYAMOTO, Mikio ISHIHARA, Junji FUJINO, Yuji IMOTO, Naoki YOSHIMATSU
  • Publication number: 20160104651
    Abstract: A power semiconductor device includes an insulating substrate, a semiconductor element, a case, and a wiring member. The case forms a container body having a bottom surface defined by a surface of the insulating substrate, to which said semiconductor element is bonded. The wiring member has a bonding portion positioned above an upper surface electrode of the semiconductor element. The bonding portion of the wiring member is provided with a projection portion projecting toward the upper surface electrode of the semiconductor element and bonded to the upper surface electrode with a solder, and a through hole passing through the bonding portion in a thickness direction through the projection portion.
    Type: Application
    Filed: June 29, 2015
    Publication date: April 14, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinsuke ASADA, Naoki YOSHIMATSU, Yuji IMOTO, Yusuke ISHIYAMA, Junji FUJINO
  • Publication number: 20160099224
    Abstract: A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern.
    Type: Application
    Filed: June 29, 2015
    Publication date: April 7, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naoki YOSHIMATSU, Yusuke ISHIYAMA, Taketoshi SHIKANO, Yuji IMOTO, Junji FUJINO, Shinsuke ASADA
  • Patent number: 9307260
    Abstract: An image decoding apparatus (100) capable of appropriately executing parallel decoding processing by a simple structure includes: a stream segmentation control unit (140) that designates a processing target area, and selects a portion of a segment stream based on a position of the processing target area; M stream segmentation units (130) that generate M×N segment streams by executing stream segmentation processing on designated M processing target areas in parallel; and N decoding engines (120) that decode respective portions of the N segment streams including the selected portion in parallel. In the case where a slice included in the processing target area is segmented into a plurality of slice portions and assigned to a plurality of segment streams, each stream segmentation unit (130) reconstructs, for each segment stream, a slice portion group made up of one or more slice portions assigned to the segment stream, as a new slice.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: April 5, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoki Yoshimatsu, Takeshi Tanaka, Keiichi Kurokawa
  • Publication number: 20150380274
    Abstract: Entry of resin into a cylindrical electrode can be suppressed without excessively increasing the number of parts and without unnecessarily damaging members. For this purpose, a semiconductor chip and a cylindrical electrode are mounted on one main surface of substrate. The substrate, the semiconductor chip, and the cylindrical electrode are sealed with resin material such that the cylindrical electrode has one end mounted to the substrate and the other opposite end at least exposed. After the step of sealing, an opening extending from the other end of the cylindrical electrode to a cavity in the cylindrical electrode is formed. Before performing the step of forming an opening, the other end of the cylindrical electrode is closed.
    Type: Application
    Filed: March 23, 2015
    Publication date: December 31, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoki YOSHIMATSU, Kiyohiro UCHIDA, Taketoshi SHIKANO, Masayoshi SHINKAI
  • Patent number: 9185406
    Abstract: An image decoding device for increasing decoding efficiency and reducing the number of memory accesses includes a division unit dividing a picture into first and second coded image data; and first and second decoding units decoding, in parallel, the first and second coded image data and storing decoding results into a frame storage unit. The first and second decoding units decode the first and second coded image data using second and first decoding result information, respectively, and store the resulting first and second decoding result information into an information storage unit. When decoding a target macroblock, each of the first and second decoding units performs image processing on the corresponding second or first decoding result information indicating part of the decoded macroblock included in the macroblock line adjacent to the macroblock line including the target macroblock, and the target macroblock.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: November 10, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Tanaka, Naoki Yoshimatsu, Keiichi Kurokawa, Daisuke Iwahashi