Patents by Inventor Naoko KIFUNE

Naoko KIFUNE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11150813
    Abstract: A memory system includes a non-volatile memory and a memory controller. During a read operation to read data stored in the non-volatile memory as an N-dimensional error correction code, where N is two or more, the memory controller performs an error correction process on the N-dimensional error correction code iteratively, the error correction process including a first decoding process on a first decoding input to produce a first decoding output and a second decoding process on a second decoding input to produce a second decoding output. During the error correction process, upon determining that errors remaining in the second decoding output after a most recent iteration would not be correctable, the memory controller performs a next iteration using a first decoding input for the next iteration, which is a modified form of the second decoding output of the most recent iteration.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoko Kifune
  • Patent number: 11025281
    Abstract: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 1, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Naoko Kifune, Hironori Uchikawa
  • Publication number: 20210091792
    Abstract: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 25, 2021
    Inventors: Naoko KIFUNE, Hironori UCHIKAWA
  • Patent number: 10908994
    Abstract: A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naoko Kifune, Hironori Uchikawa, Takahiro Fujiki, Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga
  • Publication number: 20200301777
    Abstract: A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Naoko Kifune, Hironori Uchikawa, Takahiro Fujiki, Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga
  • Publication number: 20200089417
    Abstract: A memory system includes a non-volatile memory and a memory controller. During a read operation to read data stored in the non-volatile memory as an N-dimensional error correction code, where N is two or more, the memory controller performs an error correction process on the N-dimensional error correction code iteratively, the error correction process including a first decoding process on a first decoding input to produce a first decoding output and a second decoding process on a second decoding input to produce a second decoding output. During the error correction process, upon determining that errors remaining in the second decoding output after a most recent iteration would not be correctable, the memory controller performs a next iteration using a first decoding input for the next iteration, which is a modified form of the second decoding output of the most recent iteration.
    Type: Application
    Filed: February 28, 2019
    Publication date: March 19, 2020
    Inventor: Naoko KIFUNE
  • Patent number: 10452476
    Abstract: According to an embodiment, a memory system includes: a test pattern decoding unit that detects an intermediate decoding word from a plurality of test patterns; a Euclid distance calculating unit that calculates a Euclid distance between the intermediate decoding word and a received word; and a maximum likelihood decoding word selecting unit that maintains a maximum likelihood decoding word candidate. In a case where a Euclid distance of the intermediate decoding word is shorter than a Euclid distance of the maximum likelihood decoding word candidate, the maximum likelihood decoding word selecting unit updates the maximum likelihood decoding word candidate by using the intermediate decoding word and the test pattern decoding unit does not execute decoding of a test pattern having no possibility that the Euclid distance of the intermediate decoding word becomes shorter than the Euclid distance of the maximum likelihood decoding word candidate.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 22, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Naoko Kifune, Hironori Uchikawa, Daiki Watanabe
  • Patent number: 10333558
    Abstract: According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Naoko Kifune, Hironori Uchikawa, Daiki Watanabe
  • Publication number: 20190087265
    Abstract: According to an embodiment, a memory system includes: a test pattern decoding unit that detects an intermediate decoding word from a plurality of test patterns; a Euclid distance calculating unit that calculates a Euclid distance between the intermediate decoding word and a received word; and a maximum likelihood decoding word selecting unit that maintains a maximum likelihood decoding word candidate. In a case where a Euclid distance of the intermediate decoding word is shorter than a Euclid distance of the maximum likelihood decoding word candidate, the maximum likelihood decoding word selecting unit updates the maximum likelihood decoding word candidate by using the intermediate decoding word and the test pattern decoding unit does not execute decoding of a test pattern having no possibility that the Euclid distance of the intermediate decoding word becomes shorter than the Euclid distance of the maximum likelihood decoding word candidate.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Naoko KIFUNE, Hironori UCHIKAWA, Daiki WATANABE
  • Publication number: 20180278273
    Abstract: According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Naoko KIFUNE, Hironori UCHIKAWA, Daiki WATANABE
  • Patent number: 9548107
    Abstract: A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by reading operations using a first to a third read levels. A second bit different from the first bit is established by reading operations using a fourth to a seventh read levels. A third bit different from the first and second bits is established by reading operations using an eighth to an eleventh read levels. A fourth bit different from the first to third bits is established by reading operations using a twelfth to a fifteenth read levels.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 17, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoko Kifune, Masanobu Shirakawa, Ryo Yamaki, Osamu Torii
  • Publication number: 20170011795
    Abstract: A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by reading operations using a first to a third read levels. A second bit different from the first bit is established by reading operations using a fourth to a seventh read levels. A third bit different from the first and second bits is established by reading operations using an eighth to an eleventh read levels. A fourth bit different from the first to third bits is established by reading operations using a twelfth to a fifteenth read levels.
    Type: Application
    Filed: December 9, 2015
    Publication date: January 12, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoko KIFUNE, Masanobu SHIRAKAWA, Ryo YAMAKI, Osamu TORII