Patents by Inventor Naoko Nakayama

Naoko Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11609635
    Abstract: An environmental condition storage device is usable to store an environmental condition. The environmental condition storage device includes an environmental condition acquisition unit, a tactile information acquisition unit, and a storage unite. The environmental condition acquisition unit acquires an environmental condition including at least one of a temperature, humidity, wind, a picture, an image, and a sound. The tactile information acquisition unit acquires tactile information indicating a tactile sensation. The storage unit stores the environmental condition and the tactile information in association with each other.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: March 21, 2023
    Assignee: Daikin Industries, Ltd.
    Inventors: Naoko Nakayama, Sanae Kagawa, Kazuyuki Satou, Ryuta Ueda, Hideyuki Takahashi, Hiroshi Ishiguro, Midori Takama, Yuichiro Yoshikawa, Yutaka Nakamura, Hisashi Ishihara
  • Patent number: 11328174
    Abstract: A cluster classification device includes an environmental condition acquisition unit, a classification unit, and a storage unit. The environmental condition acquisition unit acquires an environmental condition in order to generate a specific environment in a target space. The classification unit generates a cluster from a plurality of environmental conditions acquired by the environmental condition acquisition unit, based on features of the environmental conditions. The storage unit stores the cluster and a feature of the cluster in association with each other. An environment generation device generates, using an environmental condition classified by the cluster classification device, a predetermined environment in the target space. An environment generation system includes the cluster classification device and a control device that controls an environment generation device that generates a specific environment in the target space.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 10, 2022
    Assignee: Daikin Industries, Ltd.
    Inventors: Naoko Nakayama, Sanae Kagawa, Kazuyuki Satou, Ryuta Ueda, Hideyuki Takahashi, Hiroshi Ishiguro, Midori Takama, Yuichiro Yoshikawa, Yutaka Nakamura
  • Publication number: 20220066561
    Abstract: An environmental condition storage device is usable to store an environmental condition. The environmental condition storage device includes an environmental condition acquisition unit, a tactile information acquisition unit, and a storage unite. The environmental condition acquisition unit acquires an environmental condition including at least one of a temperature, humidity, wind, a picture, an image, and a sound. The tactile information acquisition unit acquires tactile information indicating a tactile sensation. The storage unit stores the environmental condition and the tactile information in association with each other.
    Type: Application
    Filed: January 10, 2020
    Publication date: March 3, 2022
    Inventors: Naoko NAKAYAMA, Sanae KAGAWA, Kazuyuki SATOU, Ryuta UEDA, Hideyuki TAKAHASHI, Hiroshi ISHIGURO, Midori TAKAMA, Yuichiro YOSHIKAWA, Yutaka NAKAMURA, Hisashi ISHIHARA
  • Publication number: 20210312226
    Abstract: A cluster classification device includes an environmental condition acquisition unit, a classification unit, and a storage unit. The environmental condition acquisition unit acquires an environmental condition in order to generate a specific environment in a target space. The classification unit generates a cluster from a plurality of environmental conditions acquired by the environmental condition acquisition unit, based on features of the environmental conditions. The storage unit stores the cluster and a feature of the cluster in association with each other. An environment generation device generates, using an environmental condition classified by the cluster classification device, a predetermined environment in the target space. An environment generation system includes the cluster classification device and a control device that controls an environment generation device that generates a specific environment in the target space.
    Type: Application
    Filed: September 30, 2019
    Publication date: October 7, 2021
    Inventors: Naoko NAKAYAMA, Sanae KAGAWA, Kazuyuki SATOU, Ryuta UEDA, Hideyuki TAKAHASHI, Hiroshi ISHIGURO, Midori TAKAMA, Yuichiro YOSHIKAWA, Yutaka NAKAMURA
  • Patent number: 8582844
    Abstract: Extraction means configured to extract a blood vessel region from medical image data, detection means configured to perform evaluation regarding the shape or signal value distribution information in the periphery of a blood vessel including blood vessel contour points and the margin of blood vessel contour points in the blood vessel region extracted by the extraction means and detecting an abnormal portion on the basis of the evaluation result, and display means configured to display information regarding the abnormal portion detected by the detection means are provided.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: November 12, 2013
    Assignee: Hitachi Medical Corporation
    Inventor: Naoko Nakayama
  • Publication number: 20110235878
    Abstract: Extraction means configured to extract a blood vessel region from medical image data, detection means configured to perform evaluation regarding the shape or signal value distribution information in the periphery of a blood vessel including blood vessel contour points and the margin of blood vessel contour points in the blood vessel region extracted by the extraction means and detecting an abnormal portion on the basis of the evaluation result, and display means configured to display information regarding the abnormal portion detected by the detection means are provided.
    Type: Application
    Filed: November 10, 2009
    Publication date: September 29, 2011
    Inventor: Naoko Nakayama
  • Publication number: 20110073603
    Abstract: The storage case has a structure in which a sample storage case (S) contained in a storage case is cooled and held at a low temperature by a Stirling refrigerator. A detection element is disposed in a room-temperature area of the storage case. The chemical or physical property of the detection element varies when a contaminant adheres to the detection element. Entrance of a contaminant into the storage case can be checked by contactlessly checking the detection element from the outside of the storage case. The storage case includes a server for receiving the result of the check from the detection device, storing the result, and setting up connection via a communication line to at least two out of a terminal operable by the forwarder, a terminal operable by the carrier, and a terminal operable by the recipient to transmit the result to the two.
    Type: Application
    Filed: April 20, 2009
    Publication date: March 31, 2011
    Applicant: HITACHI, LTD.
    Inventors: Norihide Saho, Mami Hakari, Hiroyuki Tanaka, Sachi Tanaka, Yoshihito Yasukawa, Akira Nomiyama, Shinjiro Saito, Azusa Amino, Daisuke Matsuka, Kohtaro Chiba, Hiroyuki Toyoda, Naoko Nakayama, Isao Kitagawa, Isao Hagiya
  • Patent number: 6873019
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: March 29, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Jiro Ida, Naoko Nakayama
  • Patent number: 6750498
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: June 15, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Jiro Ida, Naoko Nakayama
  • Patent number: 6734507
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: May 11, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Jiro Ida, Naoko Nakayama
  • Patent number: 6521955
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 18, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Jiro Ida, Naoko Nakayama
  • Publication number: 20030015746
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.
    Type: Application
    Filed: September 18, 2002
    Publication date: January 23, 2003
    Inventors: Jiro Ida, Naoko Nakayama
  • Publication number: 20030015747
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.
    Type: Application
    Filed: September 18, 2002
    Publication date: January 23, 2003
    Inventors: Jiro Ida, Naoko Nakayama
  • Publication number: 20030015748
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic suicide layer.
    Type: Application
    Filed: September 18, 2002
    Publication date: January 23, 2003
    Inventors: Jiro Ida, Naoko Nakayama
  • Patent number: D1015879
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 27, 2024
    Assignee: KOSE CORPORATION
    Inventors: Yusuke Nakayama, Naoko Akai