Patents by Inventor Naoko Numata

Naoko Numata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190067177
    Abstract: A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the package substrate and includes a semiconductor element. An adhesive is provided between the semiconductor chip and the package substrate. A metal bump is provided on the second surface. A package substrate is a multilayer substrate that includes first to fourth wiring layers and first to third resin layers. CTE1<CTE2<CTE3<CTE4 is satisfied where coefficients of thermal expansion of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are CTE1 to CTE4, respectively. EM1>EM3>EM2>EM4 is satisfied where elastic moduli of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are EM1 to EM4, respectively.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 28, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akira TANIMOTO, Hideko MUKAIDA, Naoko NUMATA, Kenji MIYAWAKI
  • Patent number: 10217701
    Abstract: A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the package substrate and includes a semiconductor element. An adhesive is provided between the semiconductor chip and the package substrate. A metal bump is provided on the second surface. A package substrate is a multilayer substrate that includes first to fourth wiring layers and first to third resin layers. CTE1<CTE2<CTE3<CTE4 is satisfied where coefficients of thermal expansion of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are CTE1 to CTE4, respectively. EM1>EM3>EM2>EM4 is satisfied where elastic moduli of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are EM1 to EM4, respectively.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akira Tanimoto, Hideko Mukaida, Naoko Numata, Kenji Miyawaki