Abstract: A probe card has a thin film substrate having projection electrodes on a first surface facing the semiconductor wafer and at a position facing the pad electrodes, a non-contact electrode, and first electrodes provided a second surface opposite to the first surface; and a wiring substrate having second electrodes disposed at a side opposite to the semiconductor wafer in the thin film substrate and at a position facing the first electrodes. The wiring substrate and the thin film substrate form a first sealed space and the thin film substrate and the semiconductor wafer form a second sealed space. By reducing the pressure in the first and the second sealed space, the first and the second electrodes are brought into close contact with each other and the pad electrodes and the projection electrodes are brought into close contact with each other, and the pressure of each of the first and second sealed space can be independently adjusted.

Abstract: A probe comprises: a membrane having a bump which contacts an input/output terminal of an IC device built into a semiconductor wafer under test; a pitch conversion board having a bottom surface on which a first terminal is provided and a top surface on which a second terminal connected to the first terminal is provided; a circuit board which is electrically connected to a test head and has a third terminal; a first anisotropic conductive rubber member having a first conductor part which electrically connects the bump of the membrane and the first terminal of the pitch conversion board; and a second anisotropic conductive rubber member having a second conductor part which electrically connects the second terminal of the pitch conversion board and the third terminal of the circuit board, and the second conductor parts are provided on the whole of the second anisotropic conductive rubber member.

Abstract: A probe card has a thin film substrate having projection electrodes on a first surface facing the semiconductor wafer and at a position facing the pad electrodes, a non-contact electrode, and first electrodes provided a second surface opposite to the first surface; and a wiring substrate having second electrodes disposed at a side opposite to the semiconductor wafer in the thin film substrate and at a position facing the first electrodes. The wiring substrate and the thin film substrate form a first sealed space and the thin film substrate and the semiconductor wafer form a second sealed space. By reducing the pressure in the first and the second sealed space, the first and the second electrodes are brought into close contact with each other and the pad electrodes and the projection electrodes are brought into close contact with each other, and the pressure of each of the first and second sealed space can be independently adjusted.

Abstract: According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit 113 from the outside are compared with each other in an expected value decision circuit 114, the sum being outputted from the output compression circuit 112, a pass/fail decision result obtained by the comparison can be outputted from an output terminal 116 of the expected value decision circuit 114 to the outside, and the decision result can be stored regardless of the reset of a system.

Abstract: The connection between a PTC element 22a corresponding to each semiconductor IC 11a and a power-supply line 25a is performed via a relay, a high voltage is supplied to the power-supply line 25a by sequentially turning on the relays, and a high voltage is supplied to each PTC element 22a in order, whereby it is possible to trip beforehand a PTC element 22a connected to a DC-defective semiconductor IC 11a. In this state, wafer level burn-in is performed together, which enables the PTC element 22a to be positively tripped during the burn-in for the DC defect of the semiconductor IC 11a, with the result that it is possible to increase the reliability of the burn-in.

Abstract: The connection between a PTC element 22a corresponding to each semiconductor IC 11a and a power-supply line 25a is performed via a relay, a high voltage is supplied to the power-supply line 25a by sequentially turning on the relays, and a high voltage is supplied to each PTC element 22a in order, whereby it is possible to trip beforehand a PTC element 22a connected to a DC-defective semiconductor IC 11a. In this state, wafer level burn-in is performed together, which enables the PTC element 22a to be positively tripped during the burn-in for the DC defect of the semiconductor IC 11a, with the result that it is possible to increase the reliability of the burn-in.

Abstract: According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit 113 from the outside are compared with each other in an expected value decision circuit 114, the sum being outputted from the output compression circuit 112, a pass/fail decision result obtained by the comparison can be outputted from an output terminal 116 of the expected value decision circuit 114 to the outside, and the decision result can be stored regardless of the reset of a system.

Abstract: The connection between a PTC element 22a corresponding to each semiconductor IC 11a and a power-supply line 25a is performed via a relay, a high voltage is supplied to the power-supply line 25a by sequentially turning on the relays, and a high voltage is supplied to each PTC element 22a in order, whereby it is possible to trip beforehand a PTC element 22a connected to a DC-defective semiconductor IC 11a. In this state, wafer level burn-in is performed together, which enables the PTC element 22a to be positively tripped during the burn-in for the DC defect of the semiconductor IC 11a, with the result that it is possible to increase the reliability of the burn-in.

Abstract: A semiconductor test device comprises a substrate having a opposed-wafer surface on which a semiconductor wafer with a plurality of the embedded semiconductor devices is placing opposite when a burn-in test is implemented, a wiring layer provided on the substrate, and a temperature sensor for measuring a temperature of the semiconductor wafer in the state here the semiconductor wafer is placing opposite on the substrate, wherein the wiring layer includes a wiring which is connected to the semiconductor wafer in the state where the semiconductor wafer is placing opposite on the substrate, and supplies a signal and a voltage for the burn-in test to the semiconductor wafer, and the temperature sensor is provided on the substrate in vicinity of the opposed-wafer surface.

Abstract: An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

Abstract: An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

Abstract: A voltage level of an output node is reversed by an inverter. An output of the inverter is used as an initial setting signal. A feedback switching transistor is also provided in an initial value setting circuit. Furthermore, there is provided a limiting device for eliminating an abnormal operation of the feedback switching transistor until the inverter starts a normal operation, in the event of momentary power failure or when the electric power source is quickly turned on after a very short break. Accordingly, normal operation of the inverter is assured even in such an abnormal condition accompanying momentary interruption of power supply, thereby surely outputting an initial setting signal.

Abstract: A current mirror is composed of N-MOS transistors N1, N2, a diode-connected P-MOS transistor P1 is connected to an output side of the current mirror, and a source of a P-MOS transistor P2 controlled according to the gate potential of the P-MOS transistor P1 is connected to a power source V.sub.CC via a polysilicon resistor R. The drain of the P-MOS transistor P2 is connected to the drain of the N-MOS transistor N2. A current-mirror-connected N-MOS transistor N3 is provided at the current mirror of the N-MOS transistors N1, N2. The output of the N-MOS transistor N3 is inputted to another current mirror composed, on the power source V.sub.CC side, of two P-MOS transistors P3, P4, a constant current is outputted from the drain of one of the two P-MOS transistors P3, P4 and received by a load circuit which is the series-parallel connection of diode-connected P-MOS transistors P5-P8, and the voltage generated at the load circuit is outputted as a reference voltage output V.sub.REF.

Abstract: A random access memory includes a redundancy repair circuit having a plurality of parallel connected transistors and a plurality of fuses connected to respective drains of the plurality of transistors. An electrically resistive element is connected to a common node to reduce a difference in operating speeds between a first case in which the circuit is precharged from a state in which discharge to a low level was effected via one of the transistors and a case in which precharging of the circuit is effected from a state in which discharging was carried out via a plurality of the transistors.