Patents by Inventor Naotaka Hashimoto

Naotaka Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7598558
    Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Naotaka Hashimoto, Yutaka Hoshino, Shuji Ikeda
  • Patent number: 7569457
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7553766
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nishihara, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Publication number: 20080132022
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Application
    Filed: November 9, 2007
    Publication date: June 5, 2008
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Publication number: 20080090358
    Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
    Type: Application
    Filed: December 4, 2007
    Publication date: April 17, 2008
    Inventors: Shinji NISHIHARA, Shuji Ikeda, Naotaka Hashimoto, Hiroshi Momiji, Hiromi Abe, Shinichi Fukada, Masayuki Suzuki
  • Publication number: 20080061381
    Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
    Type: Application
    Filed: October 29, 2007
    Publication date: March 13, 2008
    Inventors: Naotaka Hashimoto, Yutaka Hoshino, Shuji Ikeda
  • Patent number: D578674
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 14, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D579129
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 21, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D580562
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 11, 2008
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D581062
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 18, 2008
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D581063
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 18, 2008
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D581064
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 18, 2008
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D586929
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: February 17, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D588286
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: March 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D588287
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: March 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D588288
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D595432
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 30, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D595433
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 30, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D597687
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: August 4, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda
  • Patent number: D597688
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: August 4, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinya Kawagoe, Naotaka Hashimoto, Toshiyasu Kojima, Taku Ikeda